Hi, all.
1) In my knowledge, eADR includes only up to L1 cache and not includes core's local store buffer. If system crash occured, couldn't data in store buffer survive on eADR enabled architecture?
2) In the single core system, don't I have use 'sfence' command for global visibility on eADR enabled architecture?
3) I want to know exact store buffer size, but I couldn't find it at Intel homepage. How could I know the size of store buffer? My server is:
- Intel Xeon(R) Gold 5215M CPU @ 2.50GHz
- Intel Xeon(R) Platinum 8360Y CPU 2.4 GHz
Thank for reading.
Sincerly,
Shean Kim.