CXL Write Transactions with FastGO

[Gal]

Hi all,

I have a couple of questions regarding CXL cache write transactions, I hope this is the right place to ask those. I am assuming a CXL type 2 device in the following questions, and referring to the latest version of the spec (3.0).

I am trying to understand the difference between strongly and weakly ordered write transactions.

I refer to weakly ordered writes as write transactions that are considered complete by the device when locally observable in its coherence domain (i.e., written to L1), using the FastGO option. Would it be correct to say that from a semantic point of view, these do not differ from stronger writes (namely, satisfy the same coherency guarantees)? Or, alternatively, is the meaning of the fact that cacheline state isn't transferred in this flow meant that the host is allowed to grant local ownership in the form FastGo to multiple devices (thus allowing parallel writes to the same address in different coherence domains)?

Cheers,

Gal