Is SFENCE instruction actually needed in eADR systems?

[Shaoyuan Chen]

Hi,

In the pre-eADR era, the pmem programming guideline requires to issue a SFENCE instruction after a cache line flush instruction to ensure the written data is actually flushed (and persisted) to the persistent memory before moving forward. 

With eADR, data gets persisted as soon as it enters the CPU cache, which also means the data is visible to other threads. However, in regular multi-threaded programming we almost never use SFENCE instruction (except in a few cases e.g. ntstore) to make the data globally visible thanks to the total store order (TSO) of the x86 memory model.

Considering that with eADR, the global visibility of written data is the same as the persistency, can we safely remove the SFENCE instruction in pmem programming?

Thanks,

Shaoyuan

[Oksana Sałyk]

Hi  Shaoyuan,

I recommend the following thread:
https://groups.google.com/g/pmem/c/_DJCFGylfVE/m/L0oyltg8BAAJ

Regards,
Oksana.