Persisting guarantee of core switching

[Xinwei Fu]

Hi, all!

I have a question about the persisting guarantee of CPU core switching.

Suppose we have the following code execution:

STORE(addr); \\ executed by CORE 1

                        \\ context switch

FLUSH(addr);  \\ executed by CORE 2

FENCE();         \\ executed by CORE 2

What is the persisting guarantee of STORE(addr),

(1) if CORE 1 and CORE 2 are within the same socket and LLC?

(2) if CORE 1 and CORE 2 have different sockets and LLCs?

Thanks,

-Xinwei

--

Xinwei (Mason) Fu

PhD student, Computer Science, 2016-?

Virginia Tech

http://people.cs.vt.edu/~fuxinwei/

[Andy Rudoff]

Hi Xinwei,

The instruction sequence provides the same semantics regardless of interrupts, context switching, or which CPU each instruction works on.  For the example you gave, it works because of cache coherency and flush instructions like CLWB use the cache coherency logic to find the line and flush it regardless of which cache it is in.  If the context switch happened one instruction later, it would also still work because context switches are serializing events which have the same effect as the SFENCE in your example.

-andy

[steve]

Hi all,

Are there instructions on how to run pmembench to get data on latencies when accessing records from, e.g., a billion record hash table containing
8-byte keys and 150-byte values?

What I'm looking for is the ability to measure single-threaded latencies for transactional and non-transactional operations after the database is
populated, e.g., 50% read, 50% read and update.

Thanks!
------------
Steve Heller