I'm modifying a software stack to be persistent memory aware and have the following query on failure atomicity:
The USENIX article (Vol. 42, 2017) from Andy Rudoff mentions - "On Intel, only an 8-byte store, aligned on an 8-byte boundary, is guaranteed to be failure atomic. Anything larger than 8 bytes can be torn by power failure".
What about naturally aligned stores that are smaller than 8 bytes, for instance, a 4-byte store, aligned on a 4-byte boundary?
The Intel Software Developer's Manual (Volume 3, section 8.1.1) provides a list of memory operations that will be carried out atomically by various Intel processor families. What is the applicability of these rules for a Intel Optane DC PMM sitting on the memory bus?
Please clarify...
Thanks,
Nabeel