/*
* If the event requires a 'cachestate' qualifier but was not
* specified by the user, use a sensible default.
*/
switch (pe) {
case PMC_EV_IAP_EVENT_28H: /* Core, Core2, Atom */
case PMC_EV_IAP_EVENT_29H: /* Core, Core2, Atom */
case PMC_EV_IAP_EVENT_2AH: /* Core, Core2, Atom */
case PMC_EV_IAP_EVENT_2BH: /* Atom, Core2 */
case PMC_EV_IAP_EVENT_2EH: /* Core, Core2, Atom */
case PMC_EV_IAP_EVENT_30H: /* Core, Core2, Atom */
case PMC_EV_IAP_EVENT_32H: /* Core */
case PMC_EV_IAP_EVENT_40H: /* Core */
case PMC_EV_IAP_EVENT_41H: /* Core */
case PMC_EV_IAP_EVENT_42H: /* Core, Core2, Atom */
case PMC_EV_IAP_EVENT_77H: /* Core */
if (cachestate == 0)
cachestate = (0xF << 8);
default:
break;
}
EVENT_77H is EXT_SNOOP, but that event does not accept a cachestate
qualifier, so hwpmc returns EINVAL if I try to use this event.
Removing the case for PMC_EV_IAP_EVENT_77H fixes the event for me.
I checked the Intel Documentation and there does not seem to be a
likely event that this was supposed to be(no Core events numbed 0x*7
or 0x7* seem to accept a cachestate qualifier).
Looking over the documentation:
* Event 77H in Table A-6 (Intel Core Architecture PMCs), does not support
a cache state qualifier.
* Event 77H in Table A-7 (Intel Atom) references Table 18-14, i.e., it
supports qualification based on cache line state.
* Event 77H in Table A-8 (Intel Core Solo and Core Duo) indicates that MESI
qualification is needed.
(I don't have documentation for later Intel CPUs handy).
So the code in libpmc needs to be changed to add a default qualifier
only for the CPUs that need it. Do you mind making a patch?
Koshy
Ryan
I tested in on a Core 2 but I don't have any systems with an Atom
processor so I can't test it there.
Ryan Stone