Register Unlock Tool

[Ezilda Newnam]

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The standalone regtool.py is a Python 3 tool to read configuration and register descriptions in Hjson and generate various output formats.Currently it can output HTML documentation, standard JSON, compact standard JSON (whitespace removed), Hjson, Verilog RTL and various forms of C header files.

The standard --help and --version command line flags are supported to print the usage and version information.Because the version includes information on libraries (which may be different between systems) reporting the version output is sometimes useful when issues are reported.

The name and brief description are required. If the swaccess key isprovided it describes the access pattern that will be used by allbitfields in the register that do not override with their own swaccesskey. This is a useful shortcut because in most cases a register willhave the same access restrictions for all fields. The reset value ofthe register may also be provided here or in the individual fields. Ifit is provided in both places then they must match, if it is providedin neither place then the reset value defaults to zero for all exceptwrite-only fields when it defaults to x.

Field names should be relatively short because they will be usedfrequently (and need to fit in the register layout picture!) The fielddescription is expected to be longer and will most likely make use ofthe Hjson ability to include multi-line strings. An example with threefields:

In all of these the swaccess parameter is inherited from the registerlevel, and will be added so this key is always available to thebackend. The RXS and ENRXS will default to zero reset value (unlesssomething different is provided for the register) and will have thekey added, but TXILVL expicitly sets its reset value as 2.

The TXILVL is an example using an enumeration to specify all validvalues for the field. In this case all possible values are described,if the list is incomplete then the field is marked with the rsvdenumkey so the backend can take appropriate action. (If the enum field ismore than 7 bits then the checking is not done.)

Registers can protect themselves from software writes by using theregister attribute regwen. When not an empty string (the defaultvalue), regwen indicates that another register must be true in orderto allow writes to this register. This is useful for the preventionof software modification. The register-enable register (call itREGWEN) must be either one bit or 4 bit in width to support a FI-protectedmulti-bit REGWEN. The default value should be true and be rw1c forpreferred security control. This allows all writes to proceeduntil at some point software disables future modifications by clearingREGWEN. An error is reported if REGWEN does not exist, contains morethan one bit, is not rw1c or does not default to true. One REGWEN canprotect multiple registers. The REGWEN register must precede thoseregisters that refer to it in the .hjson register list. An example:

The tool will normally generate the register address offset by starting from 0 and allocating the registers in the order they are in the input file.Between each register the offset is incremented by the number of bytes in the regwidth (4 bytes for the default 32-bit regwidth), so the registers end up packed into the smallest space.

Space may be held for future registers (or to match some other layout) by reserving register slots.A group containing just the reserved key can be inserted in the list of registers to reserve space.For example to reserve space for four registers between REGA and REGB (thus make REGB offset be REGA offset plus 5 times the size in bytes of a register):

In other cases, such as separating functional groups of registers, the absolute offset can be specified.The next register will have the offset specified.It is an error if the requested offset is less than the current offset.For example to place ITCR at offset 0x100:

The tool can reserve an area of the memory space for something that is not a simple register, for example access to a buffer memory.This is done with a window declaration.The window size is specified as items: where each item is a regwidth wide word.The size in bytes is thus (items * (regwidth/8)) bytes.If byte writes are supported the byte-write: "True" flag can be given.The tool will normally increment the offset to align the region based on its size.

The tool will give a warning if the size is not a power of 2.The tool will also give a warning if the window has software access other than read-only, write-only or read-write.Both of these warnings are suppressed if the description acknowledges there is something special about this window by setting unusual: "True" in the window declaration.

The tool will increment the offset to align the region based on its size.The start address is aligned such that the base item in the window is at an address with all zeros in the low bits.For instance, if the current offset is 0x104, and the window size in 32-bit words is between 0x11 and 0x20 (inclusive) (i.e. 65-128 bytes), the window base will be set to 0x180.The next register will immediately follow the window, so will be at the window base address plus the window size in bytes.

The tool can generate registers that follow a base pattern, for example when there are configuration fields for multiple instances.The base pattern defines the bits (which need not be contiguous) used for the first instance and the tool uses this to pack the required number of instances into one or more registers.

For example a fancy GPIO interrupt configuration may have 4 bits per GPIO to allow generation on rising and falling edge and a two bit enum to determine the interrupt severity.In this case the multireg can be used to build the multiple registers needed.The description below shows the fields given for GPIO0 and requests generation of 32 instances.If the registers are 32 bits wide then the tool will pack the four bit instances into four registers INT_CTRL_0, INT_CTRL_1, INT_CTRL_2 and INT_CTRL_3.

Note that the definition bits for the base instance need not be contiguous.In this case the tool will match the pattern for the other instances.For example the data bits and mask bits could be in the lower and upper parts of a register:

This section documents the usage of tags in the register Hjson file.Tags is a list of strings that could add into a register, field, or memory.It can store special information such as csr register/field exclusion, memory exclusion, reset test exclusion, etc.Adding a tag follows the string format "tag_name:item1:item2...".For example:

This section details the register generation for hardware instantiation.The input to the tool for this generation is the same .hjson file described above.The output is two Verilog files that can be instantiated by a peripheral that follows the Comportability Guidelines.

The register generation tool will generate the RTL if it is invoked with the -r flag.The -t flag is used to specify the output directory where the two files will be written.As an example the tool can be invoked from the top project directory to generate the uart registers with:

The first created file (name_reg_pkg.sv, from name.hjson) contains a SystemVerilog package definition that includes type definitions for two packed structures that have details of the registers and fields (all names are converted to lowercase).The name_reg2hw_t structure contains the signals that are driven from the register module to the rest of the hardware (this contains any required .q, .qe, and .re signals described below).The name_hw2reg_t structure contains the signals that are driven from the rest of the hardware to the register module (this contains any required .d and .de signals described below).The file also contains parameters giving the byte address offsets of the registers (these are prefixed with the peripheral name and converted to uppercase).

The second file (name_reg_top.sv) is a SystemVerilog file that contains a module (name_reg_top) that instantiates the registers.This module connects to the TL-UL system bus interface and provides the register connections to the rest of the hardware.If the register definition contains memory windows then there will be subordinate TL-UL bus connections for each window.The module signature is:

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