Microprogramming

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Bradford Miller

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Aug 23, 2026, 1:10:35 PMAug 23
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Does anyone know if any documentation and tools for microprogramming the 10 survived?

Thanks!

Lars Brinkhoff

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Aug 24, 2026, 12:47:37 AMAug 24
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Bradford Miller wrote:
Does anyone know if any documentation and tools for microprogramming the 10 survived?

Tools, yes.  ITS has the microassembler for both KL10 and KS10. 

As for documentation.  For the KL10, I expect this explains the microcode.
You may also have to check schematics to see how the code affects the hardware.

For the KS10, maybe some of these?

Clem Cole

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Aug 24, 2026, 10:37:48 AMAug 24
to Lars Brinkhoff, PiDP-10

Note that  KS and KL microarchitecture (and microcode) are VERY different.  About the only thing they have in common (besides implementing the PDP-10 ISP) is that they use the MICRO assembler.  (Which was the progenitor of MICRO2 (used for VAX & beyond), though MICRO2 isn't upward-compatible.)  The KL's ucode is entirely in RAM (D for instruction dispatch, C for control); the KS's DCODE is in ROM (Because it would "never" change, and naturally, as I have come to understand, Mr. PDP-10 found the only known bug in it...).


Be careful with terminology.  The "Front End" processor for the KS10 is an 8080 (unlike PDP-10's in the KL series), but the documentation also labels them as '8080 microcode '.


The directory: https://pdp-10.trailing-edge.com/ has SIMH tap format tapes, of number of sources, binaries and tools for the KL and KS systems.  Look for the headings labeled "KS10  specific stuff" and "KL10  specific stuff." The binaries and documentation source for the microcode for each are in the files labebled: TOPS-10 KS Microcode Sources 1.13 and  KL10 Microcode Sources V2A (442)

The program called MICRO can be found in each.


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Lars Brinkhoff

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Aug 24, 2026, 10:57:55 AMAug 24
to Clem Cole, PiDP-10
Clem Cole wrote:

the KS's DCODE is in ROM

No, it's also in RAM.  It sits in a special location on disk where the 8080 retrieves it and puts in in the KS10 control memory.  The 8080 has operator commands to write individual microcode words.

Be careful with terminology.  The "Front End" processor for the KS10 is an 8080 (unlike PDP-10's in the KL series)

The KL10 has a PDP-11/40 front end.
 

the documentation also labels them as '8080 microcode '.

DEC came to use the term microcode for the code we now call firmware.

Clem Cole

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Aug 24, 2026, 3:51:21 PMAug 24
to Lars Brinkhoff, PiDP-10
below...

On Mon, Aug 24, 2026 at 10:57 AM Lars Brinkhoff <lars.br...@gmail.com> wrote:
Clem Cole wrote:

the KS's DCODE is in ROM

No, it's also in RAM.  It sits in a special location on disk where the 8080 retrieves it and puts in in the KS10 control memory.  The 8080 has operator commands to write individual microcode words.
Sorry about the confusion.  I did say the DCODE, but you are correct: the CCODE is RAM (and is loaded by the 8080 front-end from storage); but the DCODE is in ROM .   Last winter, I asked questions of its author, one of my former colleagues from both DEC and Intel (we affectionately refer to him as Mr. PDP-10).  

cut/pasted from his email to me last March:

Yes, it reads the KS ucode. [.. my email had mentioned from RP/RM disk or TU tape...] Specifically, the CCODE, since the DCODE is in ROM.  There are several variants.  Originally, one UCode that supported both KI and KL paging, as selected by the OS.  (KL is KL pointers and page tables, but only section 0 and some KL paging/extended instructions.  To support TOPS-10/KL paging, I also suppress updating the CST if the CSB is 0 - so unlike the KL, the KL paging ucode is the same for both OSs.)

When I added the byte-swapping BLTs, I split it into a KI-only (needed for diagnostics) and KL-only (TOPS20, and later TOPS-10 when I switched TOPS10 to KL paging).  Necessary for space.  But if you expanded the CCODE store, you could compile for both, and one FPGA implementation apparently did.

MIT has a variant that supports (only) ITS paging.  (And calls me an idiot in the comments...)

That last line is more than assuming.  He's one of the smartest people I know, and has an extremely deep understanding of how computers should work in theory, how they work in practice, and most importantly, why those are often different.   [He is also one of the unsung heroes of Alpha's BTW.  I think the only thing WRT Alpha I and a few other folks from UNIX-land disagreed with him on — and was later (sadly) proven right about — was the lack of byte support — EV5 finally added those instructions, as in practice, leaving everything as words had proved too painful].


Eric Smith

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Aug 24, 2026, 7:26:46 PMAug 24
to Clem Cole, Lars Brinkhoff, PiDP-10
Not only is the KS10 CCODE in RAM, but DEC found the SRAM of the day to be less reliable than might be hoped, so it is parity checked. If a parity error occurs, the CPU is halted while the 8080 front end reloads the microcode, then resumes. DEC patented this feature.

Eric


Lars Brinkhoff

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Aug 27, 2026, 1:00:31 AM (14 days ago) Aug 27
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Clem Cole wrote:
the CCODE is RAM (and is loaded by the 8080 front-end from storage); but the DCODE is in ROM.

I wasn't aware the dispatch bits are in ROM, so thank you for that information.

MIT has a variant that supports (only) ITS paging.  (And calls me an idiot in the comments...)

 It's true, there are some harsh comments.  They are mostly about the new-style IO instructions.

Lars Brinkhoff

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Aug 27, 2026, 1:20:35 AM (14 days ago) Aug 27
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By the way, Rob Doyle has made a KS10 compatible FPGA which runs the original microcode at around four times the speed.  Unfortunately there's some tricky paging issue which makes it not work fully.


(He also considered the KT20 aka "Minnow".  https://github.com/KS10FPGA/Minnow)

There's nothing at a similar level for the KL10, but Alan Mimms has made several attempts.

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