Mystery instruction, JFD

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Bill E

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Dec 1, 2025, 8:27:37 AM (2 days ago) Dec 1
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One instruction ref card I have says there is a JFD, opcode 12, but it's not implemented and it doesn't show up in other references, nor does the simh -1 version have it.
But, a G search finds:
JFD Instruction Details
  • Mnemonic: jfd
  • Operation Code: 12 (octal)
  • Action: Change fields, then set the Program Counter (PC) to the specified address (MA).
    • The instruction's 12-bit address part (bits 6-17) specifies the destination address.
    • The primary function involves interacting with the memory field system, specifically disabling the instruction field (IF).
Anyone have any info on this? The effect seems to be a direct jump using a 16 bit address, no indirect needed. That would actually be quite useful.

The 12 opcode is used by one of the strange BBN -1D instructions, also not implemented by pidp1, LCH, load character.

Bill

Bill E

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Dec 1, 2025, 8:32:06 AM (2 days ago) Dec 1
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On more inspection, what it is actually supposed to do is force a jump to bank 0 using just a 12 bit address regardless of the current bank, it's the equivalent of storing a bank 0 address and doing a jmp i thru that. So, a minor convenience but not as useful as I thought.
Bill

Norbert Landsteiner

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Dec 2, 2025, 7:35:57 AM (22 hours ago) Dec 2
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I think, this is related to the instruction/data field memory architecture of the BBN PDP-1B.

Compare the console of the BBN PDP-1B (field lights at the bottom right):

PDP1_brochMar61_p3-console.jpg

Norbert Landsteiner

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Dec 2, 2025, 7:49:45 AM (22 hours ago) Dec 2
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PS: Meaning, this is not about memory banks, as we know them, but much more similar to the PDP-8.

Best,
Norbert

Bill E

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Dec 2, 2025, 8:17:26 AM (22 hours ago) Dec 2
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Ok, that makes sense, and one reason it's not showing up in most documentation, even BBN's. They added some pretty strange instructions.
I think the -1X ones were generally more useful. Well, if you're trying to implement timesharing.

Bill

Norbert Landsteiner

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Dec 2, 2025, 8:28:19 AM (21 hours ago) Dec 2
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Yes, it's also interesting to see the evolution of the memory architecture.
  • The PDP-1A (the one with the rectangular screen and the lab bench appearance) shows now controls for any memory extension scheme, at all.
  • Then, the BBN PDP-1B has this instruction field / data field architecture, similar to what was later used for the PDP-8, but no controls related to any address bus extension.
  • Finally, there's (a) an extended address mode, where the i-bit is used as a 13th address bit for addressing a second bank, while losing indirection, and (b) an option to extend the address bus for mountable banks (for up to 12 in total), which required an optional upgrade of the address bus.

Norbert Landsteiner

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Dec 2, 2025, 8:32:00 AM (21 hours ago) Dec 2
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> and one reason it's not showing up in most documentation, even BBN's

BTW, which BBN documentation? I seem to be missing out on this one. (At least, I don't remember on top of my head.)
Any directions?

Best,
Norbert

Bill E

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Dec 2, 2025, 8:49:34 AM (21 hours ago) Dec 2
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This one, I forget where I found it, or who sent it to me. I would have guessed it was you, apparently not.
Bill
PDP-1 supplement.pdf

Norbert Landsteiner

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Dec 2, 2025, 9:11:55 AM (21 hours ago) Dec 2
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Thank you!
I think, the PDP-1-D supplement is on Bitsavers (and I think, it's from DEC, compare the typography).

Best,
Norbert

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