How is the 16 channel break system supposed to work?

[Bill E]

I've tried 2 tests.

First one, uses pure pdp-1 instructions and is sbs16test2.mac It executes the channel breaks but it isn't saving the correct PC for channel 1. It has the addr of the isb instruction, not the following hlt, so the program just loops forever:

Second uses a dynamic IOT to initiate a channel break. Channel 0 is fine, channel 1 doesn't seem to execute even though logging shows a break on channel 1 is being requested internally. But, the PC is correct. This could be my problem in the break activation, but I don't see an issue in the code so far.

I'm not 100% sure I'm setting things up correctly, haven't seen any decent examples yet.

Oh, and how do I enable sbs16 since there's no way to do that? With a dynamically loaded IOT of course, and yes, I've confirmed it is setting the sbs16 flag in the emulator.

Bill

[Angelo Papenhoff/aap]

Yikes, very good question! i'm not sure i was able to test the 16 channel system all too well, lack of software is definitely a bit of a problem. so it's quite possible there are bugs in this. understanding how it's actually supposed to work is another challenge. i can look into it when i have more time in a few days

[Bill E]

I'm not sure how important this actually is. We don't have hardware devices that run asynchronously like the real -1. But, I'm looking at adding an asynchronous callback to the dynamic IOTs, There it could be useful if anyone actually uses the dyn IOT structure to hook up to external actual hardware. There are some other details to look at in the emulator, such as the completion status stuff. Again, could be useful for async IOTs. BTW, I'm having a blast with the dyn IOT stuff. Trivial to whip one up to do random things. I'm even using one to do logging of internal state for debugging.

Bill

[Angelo Papenhoff/aap]

I'm definitely interested in making sure the 16-channel break system works as advertised. having some new fun IO devices for this would be great. the ADX PDP-1s even had a 256 channel system. something like a TCP device might be quite fun!

[Bill E]

I tracked the problem down. The code wasn't clearing the interrupt in sbs16 mode, so the interrupt routine just kept getting called endlessly.

The fix is in defer() in pdp1.c:

// TP2
mop2379(pdp);
if(pdp->sbm && IR_JMP && pdp->epc == 0) {
if(pdp->sbs16) {
if((MB & 07703) == 1) {
mask = ~(1<<((MB&074)>>2));
pdp->b4 &= mask;
pdp->b3 &= mask;   // wje
                pdp->exd = 1;
                sbs_restore = 1;
}
} else {
if((MB & 07777) == 1) {
pdp->b3 = 0;
pdp->b4 = 0;
pdp->exd = 1;
sbs_restore = 1;
}
}
sbs_calc_req(pdp);
}
TP(2)

B4 was being properly cleared, but b3 also has to be cleared because it holds pending interrupt flags also.

There might be one more problem I might look into, but probably not I'll leave it to you to verify..

This code fragment:

   26                   / enable channel 1 and test it
   27 00106 720151          asb 100
   28 00107 720157          tst 100
   29 00110 760000          nop
   30 00111 760000          nop
   31 00112 760400      rt, hlt

enables chan 1, then tst 100 (a dynamic IOT) raises the chan 1 interrupt via pdp1.c req(pdp, chan). It works fine for chan 0, but it seems that for chan 1 without at least one more instruction following the instruction (nop in this case), the hlt stops processing before the chan 1 interrupt is actually processed. I don't know if this is correct behavior or not. Testing with isb instead of the IOT does the same thing, so you can test that way.

I've attached test4.mac that shows the problem using isb. Remove the nop just before the hlt and the chan 1 interrupt isn't processed, the AC stays zero.

You'll have to enable sbs16 yourself since you don't have dynamic IOT support. Also. the macro1 assembler doesn't know about asb, dsb, isb hence the defines.

Bill

[Bill E]

Minor correction to the hlt behavior -  makes no difference what channel it is. If a hlt directly follows a break, the break doesn't execute until a continue is done. Again, might or might not be correct, don't know.

Bill 

[Angelo Papenhoff/aap]

I finally got around to it now. pushed something to my own repo (not yet to pidp1), which i hope is correct, haven't tested yet. b3 is cleared at the same time b4 is set. the one channel system works differently in this regard

[Angelo Papenhoff/aap]

Also went looking into the 256 channel seq break system. it's really kinda confusing to have three different break systems in different machines with spotty schematics.

* standard: 1 channel sequence break. control logic on the SH/RO logic drawing, except the machines we have schematics for don't have it, so it's missing, oops. maybe CHM can help?

* type 20: 16 channels. both PDP-1Ds (#45 and #48) have this but because these are timesharing machines the whole wiring is somewhat different from a 1C, still helpful

* ADX machines (PDP-1C): 256 channels. and that system works a bit differently from the 16 channel one, at least we have schematics

So far I only aim to implement the first two systems but playing with 256 channels might be fun too :)

Also looking into high speed break cycles right now but again i have to compare two sets of schematics. great fun but will take a while.

It's not always easy to untangle what differences are due to C/D, plain evolution of the logic, and what is due to the different break system.

Mostly i need tests for everything, but i think you probably have something (not checked yet)

[Angelo Papenhoff/aap]

As I'm progressing further on the channel break system something weird popped up:

it seems to be impossible to clear the b2 flip-flop easily in the one-channel system. the manual says cbs clear b3 and b4, and the SC pulse (when you start the machine) clears b2.

otherwise b2 is only cleared after handling the sequence break.

unfortunately we don't have schematics for the one-channel system so i don't know if anything else can clear it. but this seems very undesirable because the paper tape reader

will set b2 when reading in a tape with a BIN loader. one would have to do an awkward dance to let it jump into the handler to dismiss it. what's going on?

[Bill E]

I don't have schematics but according to the maintenance manual, a pulse to set b2 is only recognized if sbm is on. If it's on, then the interrupt will happen and that will clear b2. If it's off, b2 will never be set because the pulse from the ptr will be ignored. Also posted this on the IRC, as distasteful as that was. :)

Bill

[Angelo Papenhoff/aap]

yeah, IRC only really works when you stay connected for a while, otherwise it's more like an email i can't reply to :)

as for what you said: can you tell me where in the manual this is said? i looked into some assembly code and i'm not sure i really understand what is going on.

What is supposed to happen when there is a break request while a handler is already executing? you could make sure to be safe by leaving break mode (lsm)

but if what you say is true, then there won't be a way for the machine to ever see the second request because it will be ignored. if b2 is set anyway even if sbm is off

we can handle the two breaks sequentially and nothing is lost. but then we have the problem i stumbled over.

unfortunately we don't have any schematics for a pdp-1 with the one channel system.

a comment in simh has this to say:

```
   Questions:

        cks: which bits are line printer print done and space done?
        cks: is there a bit for sequence break enabled (yes, according
             to the 1963 Handbook)
        sbs: do sequence breaks accumulate while the system is disabled
             (yes, according to the Maintenance Manual)
```