Re: [PIC] Secondary oscillator on PIC18F4320?

[Barry Gershenfeld]

>
> > I running a PIC 18F4320 at 40 MHz using a 10 MHz crystal and the HSPLL
> > clock mode. I have another chip on my board (quadrature encoder) that
> > requires a sampling frequency clock somewhere between 10 KHz and 100
> > KHz (TBD later). Thought I could use one of the timers and a digital
> > I/O line to generate this clock in software. Thus setup Timer1 to
> > interrupt every 50 microsec., down to every 5 microsec., to toggle the
> > I/O line.
>
>
> You can probably optimize your ISR code and reach down to the 5uS
> required and less (if no other tests for IRQ are needed in the same
> handler).
> But, I would use a PWM output for your goal: have you considered that?
>

Dario is right, and I'd bet the issue is that you just read about the
timer. (It's hard for me to remember all the stuff this chip does or I'd
know the answer without having to look it up...) The missing piece is the
the "CCP" or capture/compare module. That's the other half of the
equation. It lets you do things like drive I/O pins. PWM is fine (just
have it run at 50% duty). The compare mode could probably do it too. So it
works in conjunction with a timer to get you what you want.

The good news: Set it up properly and it will free run with 0% overhead
(don't even need an interrupt!)

Barry
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[Michael Wirth]

Dario and Barry,

Thanks for the suggestions. Bingo (almost :-)

By using Timer1 in combination with compare module, CCP1, and mode
1011 (compare and trigger special event), I can almost(!) get there.
The combination gives me a high precision scalar which, when the timer
reaches the "compare" value in the CCP, does two things: it resets the
timer's count to zero so that it starts counting up again, and it sets
the CCP1IF flag. Thus the timer count is a periodic "sawtooth"
without any software intervention. But two problems:
1. I can't seem to get the RC2/CCP1/P1A pin to toggle,
2. and the CCP1IF flag down't clear itself automatically when the timer resets.

Thus it appears I still have to use an interrupt (or, worse, poll the flag).

Am I missing something here? None of the docs I have (chip datasheet,
C library routine descriptions, John Peatman's book, "Design with PIC
Microcontrollers") seems to be explicit enough to help out.

I've taken a look at using two timers to get PWM, but that doesn't
seem to remove the need for a "start of each cycle timer reset"
interrupt.

Mike

No problem, but

On Tue, Jun 8, 2010 at 4:04 PM, Barry Gershenfeld <gbar...@gmail.com> wrote:
>>
>>...

[Olin Lathrop]

Michael Wirth wrote:
> By using Timer1 in combination with compare module, CCP1, and mode
> 1011 (compare and trigger special event),

If I remember right, you wanted to have the PIC output a certain frequency
all by itself. I don't remember off the top of my head whether that's
possible with compare mode and timer 1, but usually its done with PWM mode
and timer 2.

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[Marechiare]

Michael Wirth wrote:
> By using Timer1 in combination with compare module,
> CCP1, and mode 1011 (compare and trigger special

> event), I can almost(!) get there.The combination gives

> me a high precision scalar which, when the timer
> reaches the "compare" value in the CCP, does two
> things: it resets the timer's count to zero so that it
> starts counting up again, and it sets the CCP1IF flag.
> Thus the timer count is a periodic "sawtooth" without
> any software intervention.

- 24F chips are priced almost equally to 18F.

- The hardware part to be used is called "Output Compare module".

- Take a look at the doc "dsPIC33F Family Reference Manual Section 13.
Output Compare"
http://ww1.microchip.com/downloads/en/DeviceDoc/70209A.pdf

- PWM mode is only one of multiple operating modes, probably not the
best choice for your app..

- Your mode most probably would be "Continuous Pulse mode" (Configure
the Output Compare modes by setting the appropriate Output Compare
mode
(OCM<2:0>) bits in the Output Compare Control (OCxCON<2:0>) register.)

- 13.3.2.6 CONTINUOUS PULSE MODE
1. The Output Compare (OCx) pin is driven low immediately.

2. The timer value is compared with the Output Compare (OCxR) register
and the OCx pin
is driven high on a compare match.

3. The timer value is compared with the Secondary Output Compare
(OCxRS) register and
the OCx pin is driven low on a compare match.

4. An output compare interrupt is generated on the falling edge of the OCx pin.

- Yes, you can't go "without any software intervention". On the output
compare interrupt calculate new OCxR and OCxRS values and load them.
The timer is not getting reset if I understand the datasheet
correctly.

> The combination gives me a high precision scalar which,
> when the timer reaches the "compare" value in the CCP,
> does two things: it resets the timer's count to zero so that
> it starts counting up again

You can get even higher precision as you can "software"-cascade
OCxR/OCxRS into 64bit registers.

Good Luck.

[Michael Wirth]

Olin,

Thanks for the info. Appears that I should look more carefully at PWM
with both Timer1 and Timer2.

Marechiare,

Thanks for the suggestion on using a 24F chip, but I'm already
committed to the 18F4320 for other reasons.

If nothing else, it looks like I can write a faster ISR now that I'm
using Timer1/CCP and that should suffice.

Thanks for all the help. Great group.

Mike

[Barry Gershenfeld]

With PWM mode, you don't need two timers (unless you have another feature in
mind). There's a second register that's used to set the duty cycle for PWM,
and it merely controls where in the counting sequence it will flip the pin
to the opposite state. Set to half the value of the count-to register and
you'll have 50% duty cycle.

Barry