[EE] Suggestions for QVGA color LCD driver chip

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Peter Loron

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Jan 27, 2009, 4:14:28 AM1/27/09
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I have on hand some nice QVGA (320x240) color STN touchscreen LCD
modules. 16-pin interface. Hantronix HDM3224ATS-C-JST. Here's a link
to the closest datasheet I can find:

http://www.hantronix.com/down/s3224ats-c.pdf

I'm in need of a driver chip. Can anybody suggest one that they have
used? Epson has a number of chips that look like they would work, but
Mouser wants $15 - $20 each...more than I'd like to pay.

Thanks!

- -Pete
-----BEGIN PGP SIGNATURE-----
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iEYEARECAAYFAkl+0HcACgkQ8kSp3b4WtL/vSACeOKsvZ0R48KfKrg1NHIq5kuSZ
db8An3pL2tJkKNOvMy1ajHNrJUC/3hyd
=AEEG
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Philip Pemberton

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Jan 27, 2009, 7:46:25 AM1/27/09
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Peter Loron wrote:
> I'm in need of a driver chip. Can anybody suggest one that they have
> used? Epson has a number of chips that look like they would work, but
> Mouser wants $15 - $20 each...more than I'd like to pay.

I usually use a cheap FPGA or CPLD and an external SRAM. Not really an option
if you want "turn key" but it works out a little cheaper (in terms of parts
cost) than most COTS LCD driver chips. Rig the CPLD to generate the timing for
a display 5 or 6 lines larger than yours, but disable the latch pulse during
the extra lines (the "vertical blanking interval"). Add a multiplexer and some
glue logic to allow a PIC (or similar) to take control of the SRAM during the
VBI and update the display.

320 columns * RGB = 960 bits, or 120 bytes per row; 240 rows is 28800 bytes of
RAM, so you'll need a 32Kbyte (256Kbit) SRAM.

I've had something similar working on a Xilinx XC9572XL, which can be had for
~$5. An XC95144XL (~$8-9) would probably be enough to contain the glue logic
and RAM muxes/state machine as well.

I've got some Verilog HDL code lying around that you can have a look at if you
want to go down this path...

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Phil.
pic...@philpem.me.uk
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Peter Loron

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Jan 27, 2009, 3:32:29 PM1/27/09
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Thanks for the reply. Yeah, I've seen people going that route.
However, I have zero experience with FPGA and CPLD stuff so it would
be a long slog uphill to get to the point of productivity for me.

-Pete

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