Agilex Dev Kit
Yufei Labbe
I've got multiple bit stream files I'd like to use for configuration of our agilex FPGA (AGFB014R24A2E3VR0). While the UBII and Power Max 10 chips do seam to work (the board test system shows power and clock stats) the programming (both our bitstream and the intel example bitstreams) always fails at 13% (using both the quartus programmer and the one provided by the BTS). Searching the exact error message (obtained by right click -> copy on the log message) wasn't of any help. We're using Quartus Pro 20.4 on Ubuntu 20 and Windows 10 (neither worked, both with the same issue).
thanks a lot for your help! We've fixed this issue now. One thing we'd like to share, for a potential future reader, is that in addition to the above mentioned article one needs to completely erase the flash prior to configuring. Our working solutions looks like the following:
It's also required to leave the JTAG chain in the default configuration while erasing the flash. Last but not least: If step 8 fails retry a couple of times until it stops failing (we usually don't need more than 3 tries). It also seams to be more reliable (programming fails less often) at 24MHz than 6MHz, which the programmer defaults to anyway.
Warning(19729): Current CMF data structure hash (0x15CD440C) is older version than latest CMF data structure but still allowable.
This might be transition period. You should update your CMF to latest version with hash 0x8AC9CBBA [ACDS 20.4 Release]
It should have something to do with Quartus compatibility issue from 19.x to 20.4, which means you probably fail to configure FPGA SOF 20.x again if FPGA has been configured with 19.x image right after power cycle. For devkit, it usually has an image in ASx4 flash for power-on boot-up, so if the AS programming file JIC file generated by 19.x, then it probably runs into FPGA 20.x SOF file configuration issue later on after power cycle. So there are two options to go, one is to erase ASx4 flash with Programmer, the other one is to set MSEL to JTAG only mode. BTW, please do use 19.x Programmer to configure 19.x SOF file, same to 20.x SOF file, otherwise, it may run into configuration issue as well.
from the BTS we've tried bts_config.sof and qsfpdd_xcvr_nrz_25gbps.sof as well as the GPIO example. The Bitstream we've provided above (Have a look inside Hello_World.tar.xz), initializes the I/O and toggles the GPIO and QSFP leds at 1Hz. Besides writing a bitstream generated by the golden top example, I'm out of Ideas what could be more simple.
We're using the AGFB014R24A2E3VR0 part as stated on the sticker on our dev kit. Since our last post we downgraded to Quartus 19.1 and get a different error since then (Error(18952): Error status: Synchronization failed). I've attached a recent screenshot as requested.
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