RESUME: Hardware Design Engineer
Jasjeet Singh
JASJEET SINGH
118, 1641, McKENZIE AVENUE,
VICTORIA V8N5M4
B.C., CANADA
Tel(R): (250) 472-1217
(W): (250) 721-6026
Email : jsi...@ece.UVic.CA
URL : http://www.ece.uvic.ca/~jsingh
CAREER OBJECTIVE
================
To work as a VLSI design engineer in the fields of networking,
multimedia or telecommunications.
SUMMARY OF SKILLS
=================
* Experience in ASIC design, test vector generation and writing
testbenches using VHDL and Verilog.
* Design for Testability approaches.
* Expert user of design tools SYNOPSYS, MENTOR GRAPHICS and CADENCE.
* Skilled in the design of multiprocessor systolic arrays.
* In depth knowledge of MPEG, JPEG, Wavelets, ATM, T1/E1, HDSL, ADSL
and embedded coding schemes.
EDUCATION
=========
Present : M.A.Sc candidate in Electrical and Computer Engineering,
------- University of Victoria, Victoria
Specialization : Digital ASIC design
Cumulative GPA : 8.7/9.0
Expected date of completion : December 1998
1996 : B.E. in Electrical Engineering
---- Panjab University, Chandigarh, India
WORK EXPERIENCE
===============
September 1996 - present : Research Assistant, University of Victoria
------------------------
Involved in the hardware design of a wavelet based real time image
compression coder. The coder generates a fully embedded code
ideally
suited for progressive image transmission. The coder was
implemented
in VHDL and was simulated using Mentor Graphics. Gate level
synthesis
of the design was done for an 8x8 image in Synopsys using 0.5
micron
technology.
COMPUTER SKILLS
===============
* Languages : VHDL, Verilog, C, HTML
* Environment : Windows NT 4.0, UNIX (Solaris, HP-UX)
* Packages : Synopsys, Mentor Graphics, Cadence, Matlab
AWARDS
======
* University of Victoria Fellowship, Victoria, Canada (1996-present)
* Panjab University Merit Scholarship, Chandigarh, India (1992-96)
PROJECTS
========
Title : Systolic-array architecture for 2D Wavelet transform
Description : Designed a systolic array architecture for computing the 2D
wavelet transform using space time mapping techniques. The
design was implemented in VHDL and simulated in Mentor
Graphics. Partial serial scanning testing strategy was used
to
make the design testable. Gate level synthesis was done
using Synopsys and a chip layout was obtained in Cadence
using
the 0.5 micron technology.
Tools : VHDL, Synopsys, Mentor Graphics, Cadence
Title : VHDL implementation of an ATM switch
Description : Design of an ATM switch was studied and a 4x4 switch was
implemented in VHDL. Logic verification of the design
modules
used in routing a user cell was done by writing a test-bench
and
simulating it using Mentor Graphics.
Tools : VHDL, Mentor Graphics.
PUBLICATIONS
============
* J. Singh, A. Antoniou, D. J. Shpak, "A Distributd memory and control
architecture for 2-D Discrete Wavelet Transform", submitted to
1999 IEEE International Conference on Acoustics, Speech, and Signal
processing, Phoenix, Arizona, USA.
* J. Singh, A. Antoniou, D. J. Shpak, "Hardware Implementation of a
Wavelet
based Image Compression Coder," 1998 IEEE Symposium on Advances in
Digital Filtering and Signal Processing, June 1998.
REFERENCES
==========
Available upon request
shahy...@gmail.com
what is your paper name about systolic 2d dwt ?
thanks