Showing multiple outputs in waveform

[Federico Peruzzo]

Hi everyone,

I was trying the bambu framework and I encountered some difficulties:

1. I’ve been unable to locate comprehensive documentation for the project. The only

     resources I’ve found on the project website are “Bambu:Examples, Bambu:Options,

     Bambu:Targets”. Does anyone know where I can find more detailed documentation?

2. I’m wondering if there are any flags I can set to make the outputted Verilog more

     readable, even if it means sacrificing some of the optimizations and PPAs. Any

     suggestions would be appreciated.

3. As indicated in the title, I’m trying to figure out how to simulate and display the outputs in

     waveforms. So far, the only method I’ve found involves outputting a single value as the

     return value of the top function/module in the C/C++ code. Does anyone know of a

     different approach?

Any help would be greatly appreciated. Thanks in advance!

Federico Peruzzo

[Michele Fiorito]

Hi Federico,

Unfortunately, we are a little short on documentation. Depending on what you need, you may find some information on PandA Bambu installation on https://docs.bambuhls.eu/ (which is doxygen documentation generated from the files in the repository). If you need information on the options for the synthesis, the help text is the best you can look for. You will find a short description of each option.

About the generated code, there is no way to change the formatting. The best way to look into the generated architecture is to pass the --print-dot option to Bambu HLS. This will output many graphs under the HLS_output/dot directory: here, you will find graphs for CFG, state transition graph, FSM graph, and others. Each graph includes a C-like pretty print of the operations and their Verilog instance identifier. Finally, to generate the waveform during the RTL simulation, you need to use the --generate-vcd option, which will generate a VCD file (HLS_output/simulation/test.vcd) containing waveforms for all internal signals of the simulated design.

By the way, when you provide a C/C++ testbench using the --generate-tb=<tb_file.{c,cpp}> option, Bambu HLS will automatically generate a Verilog testbench that interacts with the C/C++ testbench at runtime and also automatically compares the original C/C++ implementation output with the RTL simulation output. You can ask Bambu HLS to run the simulation automatically using the --simulate option or the generated simulate_<top_fname>.sh script.

Please let me know if you need any other information on the tool.

Best,

Michele Fiorito.