Hi,
Concerning point 1.), I think that your issue is much related to the fact that different backend tools requires different BRAM Verilog/VHDL templates.
This is addressed by allowing to customize the target device memories inferred.
Check for example files:
etc/devices/NanoXplore_devices/nx1h35S-seed.xml
etc/devices/NanoXplore_devices/nx1h35S.xml
The first one is the seed used by eucalyptus to generate the second.
In the seed file you are going to see how the description of a true dual port byte enabling ram is added to the library. The component is described in Verilog section VERILOG_PROVIDED and in VHDL VHDL_PROVIDED.
The component is described in HDL by using existing descriptions available from these xml files:
etc/lib/technology/NC_MEM_IPs.xml
etc/lib/technology/C_MEM_IPs.xml
The link to these XML files is described by means of the IP_COMPONENT tag.
In case you are not finding a suitable existing component you may directly copy the body of the Verilog or the VHDL description into the VERILOG_PROVIDED and in VHDL VHDL_PROVIDED xml sections.
Moreover, you may replace any of the components coming from the Bambu IPs library (etc/lib/technology/.xml) with this mechanism.
Concerning the point 2), I would suggest to adapt these scripts:
etc/devices/characterize_device.sh
etc/devices/characterize_all_devices.sh
Cheers,
Fabrizio
PS For the sake of completeness, Virtex 4 support has been already added since 0.9.5.
PPS which is the FPGA you are targeting?