Regarding IP integration example with multiple IPs

[Rafid Muttaki]

Hello All,

Sorry for the re-post. I have been trying to generate rtl and simulate for a design having two functions that are called in the top function. I have followed the process shown in the IP integration example in Bambu.

error -> Expected a number of cycles different from zero. Something wrong happened during the simulation!

Command used: /opt/panda/bin/bambu top.c --top-fname=top --simulate --generate-tb=test_top.xml --generate-vcd --C-no-parse=arf1.c,arf2.c module_lib.xml constraints_STD.xml

When I only generate the top rtl (no simulation), I do not get this error. However,  generated testbench when run shows incomplete results (i.e., done signal does not turn to 1).

The folder with all the c and generated Verilog codes are attached below. Can anybody please help? Thanks.

With Best Regards,

Md Rafid Muttaki