Question on outputs of panda/bambu for code generation

[François de Vieilleville]

Hello,

I would have beginner questions regarding the generated code using bambu.

If I understand correctly it can generate a verilog version of a C code, using both the CPU and the FPGA from a soc.

The choice of the functions to be put on the FPGA is done by the user through the command line interface.

My questions would be if there is a high level intermediate code decribing how the exchange of information between CPU et DRAM and FPGA and DRAM are exchanged for the chosen function to be ported on the FPGA, say maybe is a AXI bus stream object with some properties ?

Is such a description available as an output of bambu ? Or is it implicitely describing in the verilog files ?

How to retrieve this information in this case ?

Regards,

François

[Fabrizio Ferrandi]

Hello,

I've inlined the answers in the following text.

Cheers,

Fabrizio

On Friday, March 20, 2020 at 9:11:40 PM UTC+1, François de Vieilleville wrote:

Hello,

I would have beginner questions regarding the generated code using bambu.

If I understand correctly it can generate a verilog version of a C code, using both the CPU and the FPGA from a soc.

The C code is translated in Verilog/VHDL that later will become a bitstream that can be uploaded into an FPGA. How to interface the process with the top level Verilog/VHDL component is actually left to the user.

The choice of the functions to be put on the FPGA is done by the user through the command line interface.

option --top-fname=function_name 

select which C function will be used as top HW component.

 

My questions would be if there is a high level intermediate code decribing how the exchange of information between CPU et DRAM and FPGA and DRAM are exchanged for the chosen function to be ported on the FPGA, say maybe is a AXI bus stream object with some properties ?

Bambu has some support to standard interface but currently AXI protocol are not yet supported. How this automatic generated Verilog/VHDL will be attached to the main memory and to the CPU is left to the user/designer.

 

Is such a description available as an output of bambu ? Or is it implicitly describing in the Verilog files?

Verilog/VHDL plus some memory initialization files are the objects you need to consider. Currently, meta descriptions such as IP-XACT xml file are not produced by bambu.

 

How to retrieve this information in this case ?

The HDL code should have all what you need.

 

Regards,

François