How does KIM-1 addressing work?

[Jeremy Starcher]

I'm sure this is simple to people with formal education but ... I have a question.

How the heck does the expanded memory board for the PAL-1 work?

I know on the 'stock' 6502, the additional memory lines are not used so the memory "wraps around" at $2000

I know that the memory card uses (some) of the extra address lines to access memory $2000-$9FFF and the ROM card uses memory $A000---???? Can't be $FFFF.

So... how does the memory decoding let the CPU find the reset vectors at the high end of ROM?  What ROM ranges are... "shadowed?"

[GN L]

Hi Jeremy,

The key is on the RAM expansion card…

The RAM card has a 74ls145, just like the ROM card, for the address decoder, the 74145 input lower three pins connected to the upper address line from 6502 (A13, A14 and A15). For the interrupt vectors ($FFFF to $FFFA), the trick is we connect the 74145’s Q7 output (the highest address including interrupt vector) to Q0 then to the DEN line on PAL-1, not the RAM/ROM chip selector pin. So when the processor access $FFFF, the decoder will disable the expansion RAM and ROM, the PAL-1 with RAM/ROM expansions will back to the basic KIM-1 config, a 8K system.

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Best,
Liu