Since the beginning of this design in pads layout, when we create new designs rules in layout, we back annotate the rules to pads logic without any trouble. We have created a new via type (named here untented_via) in layout. Since then, when we Eco to pcb or Eco from pcb we get this message box :
The Design Rules use the following vias :
UNTENTED_VIA
Please make sure these vias are defined in PADS Layout before loading this file.
And, the rest of the eco is made correctly.
Any ideas why i get this message box?
thank you
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You, IMHO, are handling rules the easiest way, doing them in PPCB then
back annotating it to Logic rather than the other way around. It just
works easier that way.
That said there is a funky bug that comes and goes in Logic where if you
back annotate by importing a ECO file all is fine but if you back
annotate by OLE PADS Layout Connection, then press "send rules from
PPCB" you have to do this twice for all the rules to come though. I
don't know if they have ever fixed this or not, but I have been burned
by it so many times I just press the button twice out of habit now.
Hawker
your explanation sounds ok to me. If I remember right, I had created the via stack in Layout, and back annotate in logic. Then before i could save the layout file, pads layout closed with a Fatal run time error (it happens from time to time :)!). And I had to make the via stack again in layout.
I will ignore the message for now. Can it be corrected? Thank you for your input, really appreciated!
Caroline