P25 hotspot, is it possible?

[Juan Carlos Pérez]

Hi, I was wondering if it would be possible to interfase an XTL2500 to the P25NX network as a hotspot without using a Quantar repeater? Could it be possible to interface the radio thru the DB-25 connector to a Cisco and a Raspberry Pi like used on Quantars? If there is someone interested, I can contribute with testing, and debug. In the other hand, I am looking for a VHF Quantar at a good price.
Thank you,

[Alex DC5AJ]

Not possible , there is no V.24 Data at the accessory connector, not on the XTL2500 nor on any other XTL or Spectra radio.

[Bryan Fields]

On 1/28/18 10:01 AM, Juan Carlos Pérez wrote:
> Hi, I was wondering if it would be possible to interfase an XTL2500 to the
> P25NX network as a hotspot without using a Quantar repeater?

It's one of the things we're looking at using MMDVM as a channel driver.

However we've gotten a bit hung up on the v.24 to computer interface. I was
using a SPI function in a FT232 chipset, but sadly it can never run clean for
an extended period. This is due to the total lack of buffer.

I've been looking at some HDLC chipsets, but even that leaves much to be
desired. Right now the most promising is the AVR (arduino) based version.
This is intended to convert the Sync framing to Async serial and land it on a
tty at 19200 bps in Linux.

The main issue with this is sync HDLC is a bit orientated protocol and LSB
first. This leads to a number of issues trying to >> and << the incoming data
and then look for flags. Super simple to do in a shift register, very costly
in a modern CPU.

If anyone is experienced with AVR I would like to talk off list.

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[David Krauss]

Which is why when I was originally trying that, I used a rabbit embedded module which has hardware HDLC.

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[John Yaldwyn]

And why I started with the STM32 which also has a full HDLC hardware controller.

73, John ZL4JY

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[Bryan Fields]

On 1/28/18 9:04 PM, John Yaldwyn wrote:
> And why I started with the STM32 which also has a full HDLC hardware controller.

I've not seen any with a full HDLC controller that can do sync serial, async
yes, but not sync.

Do you have something under development? We have the a bunch of the network
side stuff working, it's the low level driver stuff that's been some wasted
time. Lets work together on this, I'd love to have some help.

73's

[David Krauss]

Rabbit core does sync, and I had it working but abandoned the project when the ciscos came along. I think the STM32 as well but for me at least the Rabbit was easier.

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[Bryan Fields]

On 1/28/18 10:20 PM, David Krauss wrote:
> Rabbit core does sync, and I had it working but abandoned the project when
> the ciscos came along. I think the STM32 as well but for me at least the
> Rabbit was easier.

Well at 9600 bps isn't that hard in theory with a dedicated hardware. we also
don't need to support

Basically at 16 mhz, you need to do a clock toggle every 833 cycles to make
9600 baud. then you read data on the clock low, and write it out bit by bit.
The expensive instruction is the LSB to MSB conversion.

I think there's enough processing to do this on an AVR, and output it at async
serial, which is buffered. We don't need to do checksum on it on the AVR,
this is going to be the same on the async interface.

Please if some one want's to collaborate, lets do it.

[Juan Carlos Pérez]

Hi, I worked a lot with Micrichip microprocesors using asembly code. If you can explain me more in detail what is needed I can try or if an AVR micro is the way to go, I can try that way.

[Juan Carlos Pérez]

I will start working on the HDLC inplementation on a Microchip microcontroller. I think it can be done (hoping there are enought instruction cycles to make all the stuff. I guess the Cisco can be used to test communications right? Because I do not have a Quantar yet. Only the Cisco and the v.24 board.

[John Yaldwyn]

You will find it a lot easier on the STM32 platform, there is a dedicated controller.  I don't understand why you'd want to build one in software, there is a lot more too it than a software UART.

73, John ZL4JY

On 09 February 2018 at 07:56 Juan Carlos Pérez <wodi...@gmail.com> wrote:

I will start working on the HDLC inplementation on a Microchip microcontroller. I think it can be done (hoping there are enought instruction cycles to make all the stuff. I guess the Cisco can be used to test communications right? Because I do not have a Quantar yet. Only the Cisco and the v.24 board.

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[Juan Carlos Pérez]

Great to know STM32 have a dedicated controler for HDLC. Is any model you recomend to use with that feature? I had never used STM32 so I am completely lost with that brand. So as many clues to read on an specific model will save me a lot of time searching product by product.

[Bryan Fields]

I can find many that have an asynchronous controller, but none that I can find have a bit synchronous controllers.

John, what stm32 has a sync serial controller?  If you can suggest one I'm happy to give it a try.  It will simplify so much.

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On Feb 9, 2018, at 08:46, Juan Carlos Pérez <wodi...@gmail.com> wrote:

Great to know STM32 have a dedicated controler for HDLC. Is any model you recomend to use with that feature? I had never used STM32 so I am completely lost with that brand. So as many clues to read on an specific model will save me a lot of time searching product by product.

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[John Yaldwyn]

Hi Bryan and Juan,

Seems I have miss-remembered the ST Microelectronics offerings.  The two families with built in HDLC controllers are the legacy SPEAr310 and STR710FZ1 MCU devices. Looks like HDLC did not make the cut in the STM32. Sorry, I now remember that when starting out with the STM32 I found this out a few years ago, which is why I switched to Cisco!

Dave did start out looking at the Digi Rabbit RCM 6000 CPU which does contain an HDLC controller, the details are in chapter 20 of the user manual available here:

https://www.digi.com/support/productdetail?pid=4778&type=documentation

If you really want to DIY an software HDLC here are some projects to review:

https://github.com/bang-olufsen/yahdlc

https://github.com/mengguang/minihdlc

73, John ZL4JY

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[David Krauss]

Actually, the RCM6710 module

https://www.digi.com/products/models/20-101-1319

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[Bryan Fields]

On 2/11/18 2:48 AM, John Yaldwyn wrote:
> If you really want to DIY an software HDLC here are some projects to review:
>
> https://github.com/bang-olufsen/yahdlc

Byte oriented async HDLC

> https://github.com/mengguang/minihdlc

Ditto. :(

I'd found both before, and it looks now like the second would be ideal for
doing the output from the device.

[David Krauss]

the RabbitCore is the only thing i’ve found that is reasonably cheap and does bit oriented HDLC out of the box with an easily accessible language (C).

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[Bryan Fields]

On 2/11/18 6:19 PM, David Krauss wrote:
> the RabbitCore is the only thing i’ve found that is reasonably cheap and
> does bit oriented HDLC out of the box with an easily accessible language
> (C).

Problem is, $50 for a converter is a bit steep IMO. Add in the PCB and the PI
and you're back to the same cost of a cisco :(

I think we can get a bit banging PIC or AVR to do it. It's not glamorous, but
it should be fairly straight forward.

That said, my brain is shot from Orlando, need to decompress and get some scotch.

[John Yaldwyn]

If you don't want to spend anything hack the Quantar to spit it out the unused Ethernet port. Doesn't need a full TCP stack as any EtherType will do.

Or perhaps simpler, spit it out as async on the back serial port.

John

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[David Krauss]

spend anything except a lot of time you mean !

Missed you in Orlando Hamfest this weekend John !

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[David Krauss]

$45.00. $35.00 if you want to use your own ethernet connector

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[John Yaldwyn]

Would have been great to be there!  But just back from Houston, San Antonio, Phoenix, and LA!

Yes, lots of time.  But maybe not so far fetched.  Maybe the Ethernet idea is (that's on the SCC) but maybe not hacking the 68302 wireline code to spit out the HDLC as async using the same internal serial controller but at a higher rate.

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[Bryan Fields]

On 2/11/18 11:36 PM, John Yaldwyn wrote:
> Yes, lots of time.  But maybe not so far fetched.  Maybe the Ethernet idea is
> (that's on the SCC) but maybe not hacking the 68302 wireline code to spit out
> the HDLC as async using the same internal serial controller but at a higher rate.

So, I'm not sure if you're just trolling or serious.

Quantar runs from ROM. The main CPU is a 68360, and in the 68360 you can't set
a breakpoint if running from ROM, you would need an in circuit emulator.
These are either 10,000 USD or all have been junked on the used market due to
them being 25 years old.

Even if we did, we'd need to reverse engineer the code without any source, or
symbol table, and write an IP stack. The running code (SC.O) doesn't have IP
support for anything other than firmware upgrades, and there is a rudimentary
separation between the OS and the user space programs.

The wireline doesn't do anything for the v.24 other than pass the signals to
the backplane and into the SCC2 on the SCM CPU.

So, yea, not going to happen. If we're going to go through all that, lets
rewrite the DSP code to support DMR too :)

[N4IRS]

I looked at the Ethernet but From what I read is applies to Intellipeater. Is it used in a conventional configuration?

[John Yaldwyn]

Promise I'm not trolling but exploring, OK so maybe kite flying :)

I think the V.24 frames and HDLC stack is done by 68302 CPU on the W/L cards based on data received from the SCM 68360 via the TDM bus.

As you know the '302 runs from flash memory on the W/L card. Code in the flash sets up the SCC and associated baud rate generators (there are three SCC ports). SCC1 is used for the TDM bus PCM highway connection.

What I was proposing with the W/L hack was to alter the BRG to 19,200 bps or higher (to avoid overrun with the longer 10 bit vs 8 bit output characters) and alter the V.24 SCC mode register from sync HDLC Mode 1,0 = 0,0 to async Mode 1,0 = 0,1.

The goal would be for the W/L card to spit out the V.24 we want still in HDLC but with framed characters which would allow a much simpler external adapter connection. I would hope the existing HDLC stack code would carry on unaware of the mode change. A couple of other SCC set up register bit might also need to be touched. I'm encourage because the SCC will support the normally sync DDCMP protocol in async mode (this is an old DEC protocol). I know this because years ago I designed a '302 based DDCMP adapter.

Sure a patch is huge challenge but simpler than re-writing undocumented code.

John

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[John Yaldwyn]

Correct but I was speculating that the interface might be still initiated.

John ZL4JY

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[N4IRS]

Well,

I just received my 10base2 hub so I'll be sniffing tonight.

[Bryan Fields]

On 2/12/18 1:51 PM, John Yaldwyn wrote:
> Promise I'm not trolling but exploring, OK so maybe kite flying :)
>
> I think the V.24 frames and HDLC stack is done by 68302 CPU on the W/L
> cards based on data received from the SCM 68360 via the TDM bus.

Nope, the SCC2 on the 68360 the output to v.24. If you're using the modem to
do voice and astro, the wireline will then be the source of this digital audio
over the modem. v.24 comes from the 68360.

I think this is correct, i mean I could be wrong, but I've pin'd it out before.

> As you know the '302 runs from flash memory on the W/L card. Code in the
> flash sets up the SCC and associated baud rate generators (there are three
> SCC ports). SCC1 is used for the TDM bus PCM highway connection.
>
> What I was proposing with the W/L hack was to alter the BRG to 19,200 bps
> or higher (to avoid overrun with the longer 10 bit vs 8 bit output
> characters) and alter the V.24 SCC mode register from sync HDLC Mode 1,0 =
> 0,0 to async Mode 1,0 = 0,1.
>
> The goal would be for the W/L card to spit out the V.24 we want still in
> HDLC but with framed characters which would allow a much simpler external
> adapter connection. I would hope the existing HDLC stack code would carry
> on unaware of the mode change. A couple of other SCC set up register bit
> might also need to be touched. I'm encourage because the SCC will support
> the normally sync DDCMP protocol in async mode (this is an old DEC
> protocol). I know this because years ago I designed a '302 based DDCMP
> adapter.
>
> Sure a patch is huge challenge but simpler than re-writing undocumented
> code.

Well, the major issue we have is getting the code to ignore it's checksum.
Again I've not found where this is, and how it's calculated (it's not
standard). If you have an in circuit debugger, I'd love to give it shot.

I think the path of least resistance is to get a PIC/AVR going to convert to
async.

[N4IRS]

FTP (port 21) and compressnet (port 3) are open. No problem logging in on FTP. Not much value.

[John Yaldwyn]

The V.24 connection (either the V.24 board or the Astro modem board) is via the J300 header on the W/L card which is directly connected to the SCC2 port of the W/L card's 68302.

There is a spare RS-232 / V.24 connector cabled to the chassis from the SCM but it doesn't work for HDLC.

Anyway with more recent Cisco routers like the 819 with integrated smart serial port available on eBay for $50 (plus $20 for a DCE cable) the Cisco solution is still a useful and compact option and now able to run from DC.

John

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[Juan Carlos Pérez]

It seems like if I opened the pandoras box with my first post on this thread. It is good to know there is a lot of interest on this. I expect to have code for a microcontroller next Monday.
Therorically at the moment I can listen to Quantar v.24. The next step is to talk to a Raspberry Pi via RS-232.

[Mitch KH6MP]

C819 doesn't seem to work well for the V.24, sadly.  Lots of latency/drops going one direction (IP network to Quantar).  The other direction is perfect.   I ended up swapping mine out with an 1841 and all the issues went away (config was the same on the 819, and the far end Cisco was not changed at all when I switched the 1841 in for the 819 .  I believe Dave also tried the 819 with the same results prior to my foray into it.

Anyway, great to see renewed interest in development here!

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[David Krauss]

Sadly, I agree. There’s something going on in the 819 that is making it unsuitable for this. 

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[JY]

What IOS version are you using?

73, John

---- David Krauss wrote ----

[Juan Carlos Pérez]

So finally I have the HDLC board working and connected a DIU 3000 to P25NX. Now I will be testing the Raspberry code for stability and to add features. Depending on the TG it can connect to P25NX or to the MMDVM P25 reflectors.

[David Krauss]

Great work guys!

Sent from an iPhone Xs 

On Nov 15, 2019, at 11:36 PM, Juan Carlos Pérez <wodi...@gmail.com> wrote:



So finally I have the HDLC board working and connected a DIU 3000 to P25NX. Now I will be testing the Raspberry code for stability and to add features. Depending on the TG it can connect to P25NX or to the MMDVM P25 reflectors.

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[Mitch KH6MP]

That is great.  Keep us in the loop of development.  I'd like to get back into playing with Quantars using an interface like this.

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