Modeling a NvM storage but from S/W perspective

[Carlos]

I know we can use an AADL Memory component to model the actual memory itself, but that is a H/W component. What would this look like from a S/W perspective? Here is what I mean:

Process - Processor / Virtual Processor

in/out data port connections - bus

???? - Memory

I'm trying to use separation of concerns and do not want to mix H/W and S/W on the same diagram.

[Frank Singhoff]

hello,

Le 18/07/2024 à 18:55, 'Carlos' via OSATE a écrit :

I know we can use an AADL Memory component to model the actual memory itself, but that is a H/W component. What would this look like from a S/W perspective? Here is what I mean:

what do you expect to do with your AADL model of NVM?

your AADL model would be different depending on your objectives

frank

Process - Processor / Virtual Processor

in/out data port connections - bus

???? - Memory

I'm trying to use separation of concerns and do not want to mix H/W and S/W on the same diagram.

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[jjhugu...@gmail.com]

To complement Frank’s answer

 

AADL uses memory for both HW and SW, one can add properties to specify the role of memory and distinguish logical from physical memory.

See https://ieeexplore.ieee.org/document/5773407

 

The AADL standard committee considered adding virtual memory, in addition to memory, as a category to have a separate abstraction for logical memories, it could be added for a future revision of AADL. The paper above provides a solution using properties that is a solution.

 

Regards,

 

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