Modeling memory in AADL

[MSE]

I am trying to model the memory in this schematic of an Infineon processor. Up to now I have only found two good papers that show how to model memory. Here is the link to the product summary:   Infineon-TC39xXX_TC39xXP_PB-PB-v01_00-EN.pdf.

I have modeled it as so:

    system implementation multi_core.quad
        subcomponents
            cores: processor core.impl[4];
            SRI: bus system_resource_interconnect.impl;
            SPB: bus system_peripheral_bus.impl;
        connections
            BA_SRI: bus access cores.SRI -> SRI;
            BA_SPB: bus access cores.SPB -> SPB;
    end multi_core.quad;

I suppose the green boxes below are accessible outside the processor via the bus SRI and SPB.

Does anyone know of other resources that can help me on interpreting such product data sheets and what to look for when modeling memory? What kinds of analysis can I do in OSATE out of the box?

[jjhudak]

The first question I would ask is ‘what questions do I want my model to answer?’    To that point, and since you are asking about memory and CPU concerns, the SEI OSATE distribution has the following built-in analysis that may fit your needs:

1 Component Power analysis – assess component power usage (power budget) against power supplied.  Power budgets can be assigned to individual cores.  One can also model variation in power budget based on differing workloads.

2 CPU resource budget analysis – determine if the CPU MIPS capacity can support the thread load bound to the CPU.  

3 Memory resource budget analysis – determine if budgeted memory usage of a software component (expressed by assignments to Data_Size, Code_Size, Heap_Size and Stack_Size) can be supported by specified memory capacity, e.g., RAM or ROM Memory_Size.

For more information look in OSATE -> Help -> OSATE Core Documentation -> Model Analysis –> Analysis.

4 One can also perform Bus Load Analysis - looks at the connections and virtual buses bound to buses in a system and checks that the bus has the capacity to carry the necessary data. 

You can model the L1, L2 caches to the CPU to get an idea of memory bus loads but this would be too fine-grain analysis and would be impacted by cache policies which is not considered in the OSATE analysis.  It would be more appropriate to model the main memory and the memory bus connection to the CPU.  Cache effects would be abstracted away and would be accommodated in the latency values of the main memory.  Detailed analysis of the CPU hardware architecture would be better served by tools such as cache simulators.

To some extent, it may be helpful to think of a multi-core CPU as a collection multi-processors, each with its own memory.  E.g., a highly abstracted representation of a multicore processor. 

One can then make use of binding specification in AADL to bind threads to CPUs, processes to memory, etc. in order to perform the above analysis. 

There are companies that sell additional plugin analysis tools that complement or extend those found in the OSATE distribution.  For example, CAMET library by Adventium Labs.

A number of example models related to CPU and memory analysis can be found at github:

https://github.com/osate/examples

https://github.com/OpenAADL/AADLib

Off the top of my head, I can’t point you to papers that provide examples of modeling multicore processors.

You may want to consider getting a copy of the Model-based Engineering with AADL book – chapter 7 addresses the modeling of execution platform components.

BTW, it would be more helpful to you to get a copy of the Infineon TC39XX architecture and programming data sheets located here

https://www.infineon.com/cms/en/product/microcontroller/32-bit-tricore-microcontroller/32-bit-tricore-aurix-tc3xx/aurix-family-tc39xxm-adas/sak-tc397xm-256f300s-bd/#!documents

Good Luck

J

[MSE]

Hello, 

The third analysis is the one that interests me the most. 

We currently have this problem in development where we are constantly running out of memory and need to modify the linker script so that new applications fit into the executable. We are interested in certain sections of memory, and many of these have to do with bss, data, and code sections. Looking at the documents in the link you gave helps to know where the offsets are in memory and so on, and I am hoping that I can use AADL to pre-integrate software applications before we compile and modify the linker script.

I am trying to model this processor and its memory but don't know the best way since it seems like there are multiple ways to do this. The processors' "4 GBytes (32-bit) of physical address space is divided into 16 equally sized 256MBytes segments" (page 8-2 of Architecture Document for the processor) so I am thinking of modeling this like a hierarchy of memory components. I suppose the applications I am mapping to need to be modeled as threads, each having source_size, data_size, etc.

The best way I found to model multi-core processors is in the attached paper.