From the Editor
Are we about to enter a world of weird effects in silicon? Or will silicon even survive? (Yes, we have heard that question before.) At the summer forecast meeting of analyst company Future Horizons, Europe Editor Dick Selwood heard about some of the different approaches to continuing to cram more and more transistors into a chip.
In addition, Mentor takes a look at how DRC and DFM checks break down below 28nm when done in the traditional design-then-verify flow, giving us their view on a better way to work.
We've extended the deadline for the final Journal Forum Posting competition. Post something creative and you could walk away with the final $500 amazon.com gift certificate!
Thanks as always for reading. We encourage you to share your thoughts in the new easier-to-use comments area right below the articles; don't be shy. Or you can get a lively discussion going on our new FORUMS.
Bryon Moyer - Editor, IC Journal
  
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New in the Forums
Posted on 08/24/10 at 6:23 PM by: bmoyer Posted on 08/24/10 at 6:21 PM by: bmoyer While UVM set OVM as its base, several new features are promised as additions. It is understandable that people will wait to see the impact of those additions.
For those who are not members of the Accellera VIP-TSC group standardizing UVM, you can g...
Posted on 08/20/10 at 4:01 PM by: dennisb From our recent experiences, UPF seems more wide spread - perhaps due to MENT & SNPS both supporting it. While we have inhouse found that CPF is scalable, hierarchical etc. for larger systems. Ideally I would love to have all vendors to support CPF if no...
Posted on 08/19/10 at 5:48 PM by: cvcblr |
Current Feature Articles
by Dick Selwood
Once upon a time, and a long time ago it was, a company in what was struggling to be known as Silicon Valley (Germanium Gulch never really caught on) had an order for a discontinued product. The customer was pressing, so the company ran a batch of wafers (probably one-inch wafers), but none of the end product worked. A second batch was also DoA. After a great deal of head-scratching, someone remembered that since the last successful production run, clean room staff had started wearing gloves. A third batch went through the line without gloves, and there was enough working product to meet the customer’s needs. One possible explanation was that sodium chloride emitted by the operators’ hands (even though wafers were handled with tweezers) created just enough doping at some stage to tip the process into yielding.
In those days, process development was one part technology and several parts black art. Things are different today, of course. But, if Future Horizons’ CTO, Mike Bryant, is correct, we may be going into even more weird realms of the unknown anytime soon. Read More
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DRC/DFM Signoff During Physical Design Provides Faster Time to Closure
by Ivailo Nedelchev and Alexander Volkov, Mentor Graphics Corporation
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When Things Look Suspicious
ASIC Analytic Looks for Anomalies in the EDIF File
by Bryon Moyer
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Keeping Things Safe for Work
MethodICs Introduces ProjectIC for Enterprise Project Data Management
by Bryon Moyer
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Passing the Test
Vennsa Tries to Figure Out Who Screwed Up
by Bryon Moyer
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Power vs. Thermal
Docea Makes the Peace
by Bryon Moyer
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Flexible Friends
by Dick Selwood
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On Demand
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Billion Gate Emulation with ZeBu-Server (CHALK TALK)
Running out of verification capacity? Today's huge designs demand a new solution with dramatically improved speed, capacity, and flexibility. Join Amelia Dalton as she talks with Ron Choi of Eve about the challenges of Billion-Gate emulation. (EvE)
Solving Today's Tough FPGA Design Problems (CHALK TALK)
Are your FPGAs outgrowing your tool flow? Join Amelia Dalton as she talks with Jeff Garrison of Synopsys about setting up your design tools for today's more demanding FPGAs. (Synopsys)
Introducing Synphony High Level Synthesis (CHALK TALK)
Having difficulty getting complex algorithms into hardware? Join Amelia Dalton as she chats with Chris Eddington from Synopsys about the latest advances in high-level synthesis - going directly from Matlab into optimized hardware design. (Synopsys)
Power Management in an Embedded Multiprocessor Cluster (WHITE PAPER)
Coherent microprocessor clusters, having localized instruction and data caches per CPU, require special techniques to maintain consistency between localized cache contents and their common address region. For embedded systems, designers typically apply snoop-based schemes to maintain memory coherence. This scheme introduces ownership attributes of local cache lines, which are posted throughout the cluster upon intent to use or change. (MIPS)
ZeBu™: A Unified Verification Approach for Hardware Designers and Embedded Software Developers (WHITE PAPER)
Moore’s law continues to drive both chip complexity and performance to new highs every year, and continues to stress and periodically “break” existing design flows. Fortunately for EDA users, the same shrinking geometries that make their design problems tougher are also helping to improve the performance for their EDA tools. (EvE)
FPGA - PCB Co-Design Done The Right Way (CHALK TALK)
Join Amelia Dalton as she talks with Hemant Shah of Cadence Design Systems about new ways to manage the complex issues that arise when trying to optimize pin assignments for both FPGAs and PCBs. (Cadence)
Improving Software Development Productivity With Virtual Platforms (CHALK TALK)
Are your SoC and embedded design projects increasingly dominated by software development schedules? Join Amelia Dalton as she talks with Frank Schirrmeister of Synopsys about ways to improve software development productivity using virtual platforms. (Synopsys)
Generating Functionally Equivalent FPGAs and ASICs With a Single Set of RTL and Synthesis/Timing Constraints (WHITE PAPER)
Electronic systems designers use FPGAs for their prototype implementations, taking advantage of the devices’ reprogrammability to validate hardware and software. Once the design is ready for volume production, designers are finding that certain types of ASICs—specifically, ASICs with a silicon platform and toolset that enable concurrent design with the FPGA, using identical I/Os, memory resources, and IP—help them meet power, performance, and cost targets. (Altera)
Catapult C Synthesis Designing a JPEG Compression Engine (CHALK TALK)
Amelia Dalton finds out that designing hardware with high-level languages can be both easy and fun as she and Stuart Clubb of Mentor Graphics walk you through the design of a hardware JPEG encoder using C++. (Mentor Graphics)
Crossing the Gap between Algorithm and Hardware Implementation (CHALK TALK)
In this webcast Amelia Dalton will chat with Stuart Clubb of Mentor Graphics about how C++ and Catapult C Synthesis can accelerate the design, implementation, and verification of complex system-level algorithms. In this webcast, you will learn about modeling techniques for representing bit-accurate arithmetic in C++ using Mentor Graphics' "Algorithmic C" data types. (Mentor Graphics)
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