Cannot generate .vcd with icarus verilog

[makksi]

I used the following commands to build and to run the simulations in openpiton, but the vcd file is not generated. Cannot understand why.

Build:

sims -sys=manycore -x_tiles=1 -y_tiles=1 -icv_build -clean

Sim:

sims -sys=manycore -x_tiles=1 -y_tiles=1 -icv_run uart-hello-world.s -build_id=tiles_1x1 -vcd -vcdfile=/test.vcd

[Jonathan Balkind]

That argument is not available with Icarus. You will have to edit the RTL to add the appropriate $dumpvars() or similar e.g. in manycore_top.v.pyv

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[makksi]

Thanks for your suggestion. I already tried to add the $dumpvars() code into an initial begin ..end statement inside manycore_top.v.pyv, with no success. The vcd file is not generated.

Any other suggestion?

Following the modfice code:

////////////////////////////////////////////////////////
// SIMULATED BOOT SEQUENCE
////////////////////////////////////////////////////////
initial
begin
$dumpfile("cmp_top.vcd");
$dumpvars(0, cmp_top);
//$dumpvars();
end

`ifndef VERILATOR
initial
begin
    // These are not referenced elsewhere in this module,
    // but are cross referenced from monitor.v.pyv.  Do not
    // delete
    fail_flag = 1'b0;
    stub_done = 4'b0;
    stub_pass = 4'b0;

[Jonathan Balkind]

The way I did this before looked something like this: https://github.com/Jbalkind/openpiton/blob/ao486_native/piton/verif/env/manycore/manycore_top.v.pyv#L238-L246

Thanks,

Jon

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[makksi]

Thanks Jon,

     it works perfectly! 

I just made a typo during the build sims. Thanks also for sharing your implementation in manycore_top.v.pyv which I guess allows to generate the .vcd only for Icarus Verilog and what it is also very useful using the -vcd switch which usually is not catched by sims with Icarus.