Virtex 7 Constraint File

[Devon White]

Hi,
I'm doing research at Carnegie Mellon University that uses the OpenPiton Processor. I'm currently trying to put the 4-core design onto my V707 FPGA. When trying to synthesize the design in Vivado in order to put the design on the board, I realized that the only constraint file included in the download is for the Nexys Video Board. Since it says that the design is compatible with the V707, I was wondering if there is a constraint file for this board, as trying to create one myself without great knowledge of the design would be a hassle. Thank you for your help, and please let me know if there is anything else I need to do to put the design onto this board,
-Devon White

[jbalkind]

Hi Devon,

If you make use of the protosyn script, it should perform the whole synthesis and implementation flow for you.

The command in question would be `protosyn -b vc707 -d system` and you can change the environment variables in some of the files in piton/design/xilinx/

If you run `protosyn -b vc707 -d system --to project` then it should generate you the Vivado .xpr file in build/vc707/system/vc707_system which you can then open in Vivado

Jon

[jbalkind]

As for 4 threads, you might find there are a couple of syntax errors when you try to change the thread count (I believe the macros you need are CONFIG_NUM_THREADS and THREADS_4, as well as disabling FPGA_SYN_1THREAD). Our upcoming release should hopefully fix some of that.

Jon

[Devon White]

We ran protosyn -b vc707 -d system.

A short list of the errors we found:

The constraint file included seems to be wrong.
-DDR is not set leading to an I/O Standard error.
-All of the false paths are not read. This probably causes the clock issue.
Also, not all of the IP Blocks are included.
The timing keeps failing on chipset_clk_clk_mmcm. (This is probably due to the constraint file issue)

We have been working on sorting these out. But, if you have a newer constraint file for the VC707, that would be great.

[Alexey Lavrov]

Hi Devon,

1) There is a separate constraint file for vc707, which is located in $DV_ROOT/design/xilinx/vc707/constraints.xdc.

2) DDR constraints are generated by MIG7 IP core, and not included into constraints.xdc. There shouldn't be any I/O Standard error. If you see one in Vivado's logs, please, let us know what is it.

3) False paths should be read. Let us know which are not

4) All IP blocks are specified by respective xci files and included in the project. Let us know which are not

5) Timing can fail because of non-deterministic routing and placing algorithms.

I would suggest to rerun one more time and check timing after it. Let us know which paths are failing.

We are planning to make a new release  next week, but a new constraint file can be not compatible with release 4.

Alexey

[Devon White]

On Thursday, March 30, 2017 at 1:46:43 PM UTC-4, Alexey Lavrov wrote:

1) There is a separate constraint file for vc707, which is located in $DV_ROOT/design/xilinx/vc707/constraints.xdc. We use this one.

2) DDR constraints are generated by MIG7 IP core, and not included into constraints.xdc. There shouldn't be any I/O Standard error. If you see one in Vivado's logs, please, let us know what is it. Anything that has to do with DDR

3) False paths should be read. Let us know which are not All four of them included in the constraint file

4) All IP blocks are specified by respective xci files and included in the project. Let us know which are not We only see clk_mmcm and the mig7 ipcore, nothing else.

5) Timing can fail because of non-deterministic routing and placing algorithms. We had to manually slow down the clock. However, this is probably due to the false path issue as I think those are the paths.

I would suggest to rerun one more time and check timing after it. Let us know which paths are failing.

We are planning to make a new release  next week, but a new constraint file can be not compatible with release 4.

We are now also running into issues around using more than one thread. Every time we try to do config_num_threads and Threads_4 or threads_3 or any of them it fails.
In lsu_qdp1.v
//bug2705 - speculative pick in w-cycle
wire    lmq3_pcx_pkt_vld ;
assign  lmq3_pcx_pkt_vld  =  lmq3_pcx_pkt_tmp[`LMQ_VLD] & ~lsu_ld3_spec_vld_kill_w2 ;


Also, we managed to fix the constraint file by manually adding the ddr constraints and then forcing it to use them. I suppose the MIG7 is not working? It does say that the configuration failed when I try to open it.

Specific false paths that are failing

set_clock_groups -name sync_gr1 -logically_exclusive -group chipset_clk_clk_mmcm -group [get_clocks -include_generated_clocks mc_sys_clk_clk_mmcm]
set_false_path -to [get_cells -hierarchical *afifo_ui_rst_r*]
set_false_path -to [get_cells -hierarchical *ui_clk_sync_rst_r*]
set_false_path -to [get_cells -hierarchical *ui_clk_syn_rst_delayed*]
set_false_path -to [get_cells -hierarchical *init_calib_complete_f*]

[jbalkind]

Could you tell us more about the tool versions that you're using? (With reference to the supported tools here: http://parallel.princeton.edu/openpiton/specs.html#SupportedTools) We've tried running but haven't seen the errors that you're seeing.

As I mentioned for 4 thread, I think there are probably some syntax errors that will need fixed as we haven't touched that configuration in some time. The patches in the coming release 5 should hopefully fix that up at least for the 2 thread case but I haven't looked at 4 thread yet.

Jon

[Devon White]

The differences I see are that we are using Vivado 2016.4 and ubuntu 16.04

[jbalkind]

Last time I ran on vivado 2016.4 I had to regenerate some of the ip cores. I ran `protosyn -b vc707 -d system --to project` then opened the vc707_system.xpr in Vivado. On the... IP sources? screen, some of the cores were shown as being "out of date" or something along those lines. If you right-click and regenerate them (should only take a minute) then you might get further.

Jon

[Devon White]

I did that already. However, after doing that, I just made another new project where it looks like the MIG7 is now working.
The false paths are mostly working. set_property CLOCK_DEDICATED_ROUTE BACKBONE [get_nets chipset/clk_mmcm/inst/clk_in1_clk_mmcm] still is not working.
The one thing I changed is that now I am doing -uart-dmw ddr. Which I was not before.