Controlling LEDs and switches

[Andreas Wrisley]

Hi,

How can I control the LEDs on the Genesys2 board from my application when running OpenPiton with two Ariane cores. I also would like to read the status of the switches.

From what I can see, some LEDs and switches are used. Where can I find information about which are used and for what?

Regards,

/Andreas

[Jonathan Balkind]

Hi Andreas,

We don't provide any specific control/readout mechanism. The LEDs (output wire named leds) are just assigned in system/chipset/chipset_impl. The switches are inputs in the same files (input wire named sw if I'm remembering right). You can replace the usage of either though I'd specifically watch out for the use of the uart_boot_en switch and suggest you not modify it.

Thanks,

Jon

Thanks,

Jon

--
You received this message because you are subscribed to the Google Groups "OpenPiton Discussion" group.
To unsubscribe from this group and stop receiving emails from it, send an email to openpiton+...@googlegroups.com.
To view this discussion on the web, visit https://groups.google.com/d/msgid/openpiton/6751f82b-6a13-42f5-bdfe-45772b11f2b5n%40googlegroups.com.

[Andreas Wrisley]

Hi,

Thanks for the information.

I'm quite new to all of this and trying to grasp how everything is connected and how to work with OpenPiton and Ariane (CVA6), but I guess I could implement memory mapped access to the leds and switches? Or is there another better solution?

If going memory mapped, where can I find the current memory map to be able to select an appropriate range. I have had some difficulties finding the correct addresses for the clint and uart. Searching through the code base gives different values in different locations and after some trial and error it seems I have something working.

Is there a document detailing the memory map?

Regards,

/Andreas

[Jonathan Balkind]

Hi Andreas,

That's exactly what I would expect, yeah. You could probably just make a little AXI-Lite module for reading and writing the state. That could be instantiated off-chip on the chipset for ease of implementation (you can see how eth_top works in chipset_impl as an example).

The memory map is mostly coming from devices_ariane.xml and there's one of those files per environment (e.g. one for simulation, one for each FPGA board). You could allocate some space where the MSB of the 40 bit address is 1 (i.e. 0x8000000000 or higher). Given it will be small I think you can probably find some space near the ethernet module, which should be visible in devices_ariane.xml for genesys2.

A more advanced way would be to put the module on-chip on the edge of the mesh but that would require some more modifications. Happy to discuss if it becomes of interest.

Thanks,

Jon

To view this discussion on the web, visit https://groups.google.com/d/msgid/openpiton/191331af-b790-4770-b497-8d191d979220n%40googlegroups.com.