FENCE rw, rw instruction

[Tony Thuong Truong]

Good morning Jon Balkind and all,

Thank a lot for instructions to run bare metal assembly test.

We, my son Gerald and I, have successfully to run 1 small coherency test with helps from you and other members of OpenPiton forum.

There are 3 FENCE rw, rw instructions in the test.

I have looked at the .log file. Not seen any "FENCE" or "MEMBAR" request on PCX interface.
Are these request monitored on PCX interface? If do what is the request type?

Thanks for helping and have a wonderful day.  

Tony Truong

[Jonathan Balkind]

Hi Tony,

Very glad to hear this!

Regarding fence, it is not something that leaves the core. It provides an ordering restriction that is (in CVA6/Ariane) internal to the pipeline in terms of guaranteeing e.g. that prior loads/stores have completed before the fence instruction itself can commit. This doesn't require direct coherence protocol participation so you don't see any messages over the Transaction-Response Interface (our more modern interface, though the monitors still mention PCX/CPX). Depending on which simulator you're using, you might be able to see the executed/committed riscv instructions in a separate log. I can't recall exactly which of the simulators do/don't support this mechanism off the top of my head though.

Thanks,

Jon

--
You received this message because you are subscribed to the Google Groups "OpenPiton Discussion" group.
To unsubscribe from this group and stop receiving emails from it, send an email to openpiton+...@googlegroups.com.
To view this discussion, visit https://groups.google.com/d/msgid/openpiton/47c78439-b63d-4d77-9cf5-193a3a396633n%40googlegroups.com.

[Tony Thuong Truong]

Thanks for a quick reply.
I am a new learner and I might have misunderstood the RISC V architecture here. Please correct if I am wrong.

I thought FENCE rw, rw instruction enforces the memory ordering, which should be broadcasted to system bus in order to assure data are globally visible, and wait for system level ACK, before the execution pipeline resume.
Note: I used to work on an architecture which has 2 level of barrier.
- The Light Barrier is not sent out to system bus, stopped at cache level once stores ahead of it completed.

- The Heavy Barrier is broadcasted to all memory related devices in system, making sure all memory stores, ahead of barrier from this core, are globally visible, and ACK back to requesting core.

Regards,

Tony Truong

[Tony Thuong Truong]

Good morning Jon,

I think I understood how the FENCE instruction in RISC V works now as core must wait for store's ACK, ahead of FENCE instruction, from L1,5, after Directory-based L2 received all ACKs from other L1.5, making store is globally visible.

Note: It is different from the architecture and/or implementation that I used to work.

Thank you very much for your helps. I will need more helps from you in future too :=) ....

Have a great weekend.

Tony Truong

[Jonathan Balkind]

Hi Tony,

Yep, exactly. In systems of our kind, the core will use the acknowledgement or response information to order their operations locally in the face of fences. It can save work versus having global synchronisation operations.

Happy to help further!

Thanks,

Jon

To view this discussion, visit https://groups.google.com/d/msgid/openpiton/ce88b721-7a46-47fb-a284-4f42dc6069dan%40googlegroups.com.

[Tony Thuong Truong]

Thanks Jon for explanations. 

Will Openpiton have 4 or more cores configurations?
Have a great day.

Tony Truong  

To view this discussion, visit https://groups.google.com/d/msgid/openpiton/CAJm4tWaPeYOv0ty6-a9RsnqFVu66mHMu%2Bjf3r0KtrWN6n6HNnA%40mail.gmail.com.

[Jonathan Balkind]

Hi Tony,

For sure. You can use -x_tiles=M and -y_tiles=N at simulation build time to set the number of cores in the 2D mesh. If you are running e.g. hello_world_many.c then you will also want to use these when running at simulation run time so that the compiler passes the correct arguments for the software to know how many cores there are. You may also need to use -finish_mask=11111 (however many 1s = how many cores) so the simulation harness also knows how many cores to check are passing/failing (since you might run your software on fewer than the total number of cores).

Thanks,

Jon