No of cores running when synthesizing the core ASIC flow

[Rawan Ramadan]

Hi All,

I'm trying to synthesize the core using Synopsys Design Compiler, but the problem is, it takes so much time to just transform the Verilog files to generic gates(using elaborate command). So my question is, when the core was tested for synthesis how many cores were running(so I may increase the number of cores) and how much time did it take to finish?

Thanks in advance,

Rawan 

[Jonathan Balkind]

Hi Rawan,

This is likely because you're elaborating the memories to flip flops. You may want to use a "blackbox" to replace the memories as in a regular ASIC flow you would normally have a memory compiler that you would replace the memories with. The OpenPiton ASPLOS 2016 paper has some numbers for time taken etc: http://parallel.princeton.edu/papers/openpiton-asplos16.pdf

Thanks,

Jon

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