ariane-sdk vs cva6-sdk

[Yasas Senevirathne]

Hi,

I'm trying to boot Linux on an OpenPiton multicore on FPGA. I realized there is a newer SDK repository by openhwgroup (cva6-sdk). Can cva6-sdk be used instead of ariane-sdk?

Thank you,

Yasas

[Jonathan Balkind]

cva6-sdk wouldn't have the Piton SD driver.

You may want to try this branch from my fork of ariane-sdk which simplifies the infrastructure a little: https://github.com/Jbalkind/ariane-sdk/tree/openpiton-opensbi

We do also have a newer 6.2 kernel which works: https://github.com/cohort-project/linux/tree/cva6platform6.2

Thanks,

Jon

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[Yasas Senevirathne]

Hi Jon,

Thank you! I was able to boot Linux working on a VC707 development board using the branch you provided. 

When I try to setup ethernet I get the following message:

ifconfig: SIOCGIFFLAGS: No such device

Would you happen to know why this is?

Thank you,

Yasas

[Jonathan Balkind]

Hi Yasas,

We haven't implemented ethernet support for VC707 as yet. My recollection is that the PHY chip used a different MDIO interface. On nexys video and genesys2, we had RGMII but on VC707 it was something different. The Xilinx Emaclite MAC used MII or something that we could transduce to RGMII and it would work, but for VC707 it required more work. It's been about 7 years since I dealt with this so I don't quite remember the details.

Thanks,

Jon

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[Yasas Senevirathne]

Jon, I totally understand! 

Thank you again for all the help,

Yasas

[Yasas Senevirathne]

Hi Jon, 

I hope you are doing well. I'm trying to get Linux booted on VCU118. I used the ariane-sdk fork you gave me above. However, the booting stops at "copying block0 of 1 blocks (0 %)". I looked in the group to see if there was already an existing solution and realized the conversation with a similar issue was not there anymore. Could you tell me if there is a known solution for this or point me to where I should start looking?

Thank you,

Yasas

On Monday, April 29, 2024 at 6:28:34 PM UTC-4 jbal...@ucsb.edu wrote:

[Jonathan Balkind]

Hi Yasas,

There are definitely some threads on vcu118 but I don't recall whether they were here. There was some discussion on the GitHub issues (check both open and closed) and on zulip too. Hopefully no one deleted their previous messages.

Vcu118 support is not easy if you're using SD. The electrical connection is a nightmare and the adapter generally needs manual modification. Have you read that section of the readme and the other threads on that? It won't immediately work off the shelf. I can help a little but I don't know the details of the electrical part much. I know one used ended up just going back to SPI SD because it was the only way to get good signal integrity but I think some others have had a little more luck.

Thanks,

Jon

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[Yasas Senevirathne]

Hi Jon,

Thank you for helping me out with this. I tried out possibly all the solutions that others have used to work around the electrical issue of the VCU118 board. I tried switching the resistors of the SD card adaptor, reducing the voltage of VADJ, and reducing the frequency of SD clock using the SD clock divider. Unfortunately, none of them were able to reliably solve the problem. The boot sequence stops at random places, which I assume is because of image corruption.  I tried out all these solutions on several boards as well, but still no luck. So I'm currently working on loading the image through PCIe. 

The PCIe integrated design I'm working on, I think is pretty similar to the F1 design. I'm currently using all the parameters that are used to build OpenPiton for VCU118, and replacing the memory controller with the F1 memory controller that gives a master AXI interface that can access DRAM. I exported the system as an IP and connected the IP  to a DRAM memory controller through an AXI interconnect block. I connected an XDMA AXI bridge to the interconnect so that I have an interface to DRAM. I then copy the image by memory-mapping the DRAM address space through PCIe and reset OpenPiton. This approach also did not work out for some reason. I have several questions about this approach.

1. Do you see any fundamental issues with this setup?
2. Could the memory-zeroing logic be overwriting the loaded image? From reviewing the RTL, I believe it should not.
3. What address range should the DRAM AXI interface be mapped to for the VCU118 system? I mapped it to 80000000 because the address translation from the piton interconnect to AXI did not seem to change
4. Any additional feedback or debugging suggestions would be greatly appreciated.

Thank you as always,

Yasas

[Jonathan Balkind]

Hi Yasas,

Sorry that VCU118's electrical setup has caused you so much strife. It's one of the reasons we never bought any when I set up my own lab at UCSB.

I'd suggest you take a look at the PCIe setup for U200/U250 developed by Daniel and Tianrui based on earlier BSC work as part of MEEP. It's got a BD in there and it works well. I think someone did try porting this to VCU118 but I haven't seen that code anywhere. It has a fairly simple shell and we use it all the time. You might like to join the zulip if you want to discuss the minutiae: https://github.com/PrincetonUniversity/openpiton/pull/133

There's also the much fuller featured embedded shell from BSC which supports some other Alveo boards plus many more of the peripherals (100G MAC, HBM, etc): https://github.com/PrincetonUniversity/openpiton/pull/150

Thanks,

Jon

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