Protosyn : Vivado Project not created properly

[Raphael Rowley]

Hi all,

I am trying to generate a chipset for the genesys2 with protosyn so it can eventually communicate with a taped out version of the rest of the systm. 

The initial setup (in repo root)

• setenv PITON_ROOT $PWD; source piton/piton_settings.cshrc; setenv ARIANE_ROOT $PITON_ROOT/piton/design/chip/tile/ariane
  
• (source a Vivado setup script)
• stgcc1120
• stgcc1020-rv64vg
  

I run the following command to launch protosyn

•  protosyn -b genesys2 -d chipset -c ariane --jobs 32 

[INFO]  protosyn,2.5:705: ----- System Configuration -----
[INFO]  protosyn,2.5:723: x_tiles   = 1
[INFO]  protosyn,2.5:724: y_tiles   = 1
[INFO]  protosyn,2.5:725: num_tiles = 1
[INFO]  protosyn,2.5:732: core      = ariane
[INFO]  protosyn,2.5:735: defining RTL_TILE0
[INFO]  protosyn,2.5:766: setenv RTL_ARIANE0
[INFO]  protosyn,2.5:784: network   = 2dmesh_config
[INFO]  protosyn,2.5:788: l15 size  = 8192
[INFO]  protosyn,2.5:789: l15 assoc = 4
[INFO]  protosyn,2.5:790: l1d size  = 8192
[INFO]  protosyn,2.5:791: l1d assoc = 4
[INFO]  protosyn,2.5:792: l1i size  = 16384
[INFO]  protosyn,2.5:793: l1i assoc = 4
[INFO]  protosyn,2.5:794: l2  size  = 65536
[INFO]  protosyn,2.5:795: l2  assoc = 4
[INFO]  protosyn,2.5:814: ---- Additional RTL Defines ----
[INFO]  protosyn,2.5:817: NO_RTL_CSM
[INFO]  protosyn,2.5:817: PITON_FPGA_MC_DDR3
[INFO]  protosyn,2.5:817: PITONSYS_MEM_ZEROER
[INFO]  protosyn,2.5:817: PITON_FPGA_SD_BOOT
[INFO]  protosyn,2.5:817: PITONSYS_CHIPSET_TOP
[INFO]  protosyn,2.5:817: PITON_ASIC_CHIPSET
[INFO]  protosyn,2.5:817: PITON_UART16550
[INFO]  protosyn,2.5:817: PITON_FPGA_ETHERNETLITE
[INFO]  protosyn,2.5:817: {OLED_STRING=\"Heeey!          I am a chipset  for (Open)Piton Enjoy debugging!\"}
[INFO]  protosyn,2.5:819: --------------------------------
[INFO]  protosyn,2.5:287: Building a project for design 'chipset' on board 'genesys2'
[INFO]  protosyn,2.5:912: Using 32 jobs in Vivado
[INFO]  protosyn,2.5:332: Running FPGA implementation down to bitstream generation
[INFO]  protosyn,2.5:941: Checking Project Build results
[ERROR] fpga_lib.py:344: Vivado Project was not created properly!
[ERROR] fpga_lib.py:345: Check: /export/tmp/rowley/core-v-polara-apu/build/genesys2/chipset/protosyn_logs/make_project.log

See attached for the log. Any help is appreciated.

Best regards,

Raphael Rowley

[Jonathan Balkind]

Do you have `dtc` in your path? It looks like it might be erroring there or possibly just after? Could be that or maybe the right gcc isn't being used in the Makefile that's being run?

Thanks,

Jon

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