Hi Chinmay,
It's due to which media independent interface (MII) standard the vc707's PHY chip supports. The Xilinx emaclite MAC that we use supports original MII for up to 100mb/s ethernet. The Digilent Nexys Video and Genesys2 FPGAs use PHY chips that support the newer RGMII and so we wrote a transducer between MII and RGMII so that we could connect to the PHY. Unfortunately, the vc707's PHY only supports the newer SGMII (see "10/100/1000 Tri-Speed Ethernet PHY
here: https://www.xilinx.com/support/documentation/boards_and_kits/vc707/ug885_VC707_Eval_Bd.pdf) which is clocked faster and uses differential serial links instead of the usual parallel links.
It's probably possible to transduce between MII and SGMII but I haven't seen any resources about this whereas there are a few solutions out there that work for MII to RGMII. If you make any progress in this direction please let us know as we'd also like to have ethernet on the vc707.
I'll note that the newer AXI ethernet IP core does support SGMII. It appears to require AXI4-Stream DMA for actually transmitting and receiving data though and that's something that we don't support at the moment.
Thanks,
Jon