performance matrix

[Sanchit Kashyap]

hello all 

I would like to know the default performance matrix of a single core in OpenPiton. and I would also like to calculate latency and Bandwidth from the logs How can I do that? If someone could explain that, it would be helpful. 

thanks 

[Guillem López Paradís]

Hi Sanchit,

I have some experience on calculating performances in OpenPiton: 

• By default, there are some CSRs that allow you to get the basics metrics: e.g. cycles and instructions.
• If you are interested in getting L2 accesses/misses, you could look at the performance counters that L2 offers. Check 5.4.9 Access to the L2 access counter, page 47, https://parallel.princeton.edu/openpiton/docs/micro_arch.pdf  
• You can probably extend the L2 counters and add other metrics in L2,  e.g. avg latency or bandwidth? You could probably reuse the same interface for these extra counters in L2.
• Finally, you can also check the log that OpenPiton outputs by default (sims.log), although it can get quite large depending on the application executed. I recommend using any scripting language of preference and observing the different NoC petitions of interest. However, to calculate latencies and/or bandwidth, it might be not trivial (you need to track the petition through the memory hierarchy and get the timestamps). Anyways I guess is technically possible.

For starters, I would suggest you to get cycles and L2 memory accesses to get familiar with the environment (if not already). Then, my recommendation would be to add more counters (if needed) at L2.

Regards,

Guillem     

[Sanchit Kashyap]

Could someone please explain the configuration, knobs, and switches that are used to change the buffer sizes and clock frequencies in open-piton design verification? Also, I need a list of broadly the following RTL registers and signals that are necessary for system-level (SOC/chiplet) and subsystem-level (IP)  performance throttling and optimization in openpiton.

RTL Registers:

>Instruction Queue (IQ) registers
>Data Queue (DQ) registers
>Register File (RF) registers
>Load/Store Queue (LSQ) registers

Clock Frequencies:

>Core clock frequency
>Memory clock frequency
>Interconnect clock frequency

Buffers:

>Data buffers in the memory hierarchy (L1 cache, L1.5 cache, L2 cache, etc.)
>Instruction buffers
>Data buffers in the interconnect

[Jonathan Balkind]

Sanchit,

Frequencies are set by clocks in manycore_top.v.pyv. If there are signals inside the core then you'll have to go and look in the core as that's not part of OpenPiton itself. I don't really understand what exactly you're looking for for the other items. Perhaps you could be more specific.

Thanks,

Jon

--
You received this message because you are subscribed to the Google Groups "OpenPiton Discussion" group.
To unsubscribe from this group and stop receiving emails from it, send an email to openpiton+...@googlegroups.com.
To view this discussion on the web, visit https://groups.google.com/d/msgid/openpiton/cbeb5a88-e34e-4392-bec7-17a316d43a49n%40googlegroups.com.

[Sanchit Kashyap]

can you give me the location of top testbench module which is a verilog or a SV file.

[Jonathan Balkind]

The file that I already mentioned, manycore_top.v.pyv. It is under piton/verif/env/manycore/

To view this discussion on the web, visit https://groups.google.com/d/msgid/openpiton/23d0b057-3a73-4508-bedc-0cf3293697bdn%40googlegroups.com.

[Sanchit Kashyap]

I want to force signals in the test bench can i do that and play with macros in the design?? plus i couldnt find this file in the flist so was confused to use this as my test bench file to force signals i instead used load_store_unit.sv file to force my signals but i am incurring errors in that. Please tell me what is giving me this error and how can i resolve this. I am including the Flist file as well. 

[Jonathan Balkind]

The error message is telling you that Verilator does not support the use of "force". You'll need to take another approach to realise what you're looking for.

I'm not sure I understand your question about the flist?

To view this discussion on the web, visit https://groups.google.com/d/msgid/openpiton/77201930-5b2e-48ea-8ae0-4382b5201921n%40googlegroups.com.

[Sanchit Kashyap]

Actually i am trying to change the clock values and PLL values i tried changing the delays in manycore_top.v.pyv but the values of clock don't change then i did some edits in fake PLL file still i wasn't able to change the values. Can you tell me how to change values of Clock and I also need the wave file what should i do to get the Wave file like VCD, i am using Verillator to build and run the design.

[Jonathan Balkind]

Verilator (pre v5.000) does not model timing in Verilog. You would need to change the clocks in my_top.cpp under something like piton/tools/verilator

You could also check out the verilator5 branch on my OpenPiton fork if you want to use the latest verilator which does support timing in the RTL.

Regarding waves, you probably need to add the following to your sims -vlt_build command:

-vlt_build_args=--trace -vlt_build_args=-CFLAGS -vlt_build_args=-DVERILATOR_VCD

Once those are added at build time, when you run, it should generate a waveform.

Thanks,

Jon 

To view this discussion on the web, visit https://groups.google.com/d/msgid/openpiton/4083284f-0043-45a9-ba0a-c429bfbb82c4n%40googlegroups.com.

[Sanchit Kashyap]

Can you provide me the link to it and steps to update the verilator 

You received this message because you are subscribed to a topic in the Google Groups "OpenPiton Discussion" group.
To unsubscribe from this topic, visit https://groups.google.com/d/topic/openpiton/Pjj4qSX0-zo/unsubscribe.
To unsubscribe from this group and all its topics, send an email to openpiton+...@googlegroups.com.
To view this discussion on the web, visit https://groups.google.com/d/msgid/openpiton/CAJm4tWYyJP09txeX7_F_WLXjxh29bmmkOaDHpd_Krz6BKoebmw%40mail.gmail.com.

[Jonathan Balkind]

The branch is here: https://github.com/Jbalkind/openpiton/tree/verilator-5

I will not be providing verilator installation support.

Thanks,

Jon