CVA6 using single threadid to access L1.5

[Ana Beatriz Fernandes]

Hi!

I am trying to add a custom block to OpenPiton, which communicates with CVA6 and L1.5. I was trying to force CVA6 to use a single threadid, so that my block could use the other, adding an arbiter between the two (as suggested here). However, I am finding it difficult to make this change to CVA6. I have tried some things, but currentlt simply modified this line in wt_l15_adapter.sv:

assign l15_req_o.l15_threadid = (arb_idx) ? dcache_data.tid : icache_data.tid;

to

assign l15_req_o.l15_threadid = {L15_TID_WIDTH{1'b0}};

I tried running a simple test (hello_world) and noticed everything seemed fine in the output, however the simulation wouldn't end and woud get stuck until a timeout occurred. 

Could I get some directions, or perhaps a link to similar work as I've seen in this forum that others have attempted similar implementations?

Thanks in advance,

Ana

[Jonathan Balkind]

Hi Ana,

I see (and I believe I understand) the issue you're having. I think basically that ariane would need to get a little more modification because there are some places inside where I think tid might get used? What specific issues do you see with your approach? Is it hanging immediately or is there more going on before it fails? It could be something about returning invalidations back to the caches (or similar). I saw you joined Zulip so I'm also happy to discuss in #cores/ariane there if it's easier.

We did something similar for Cohort (https://github.com/cohort-project/cohort-soc) and MAPLE (in the OpenPiton repo) but in that case the core was in a different tile so we were just arbitrating between our own modules.

Thanks,

Jon

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[Ana Beatriz Fernandes]

I have since been able to solve this issue! I just had to reduce the maximum number of D$ requests (cfg.DCACHE_MAX_TX) from 2 to 1 and force D$ to only use threadid 0 (.RdAmoTxId(0)).

Ana 

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[Jonathan Balkind]

That's awesome! I'm glad to know this is possible without a huge amount of work!!

Thanks,

Jon

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