Hi,
According to OpenPiton FPGA Prototype Manual (fpga_man):
Interrupts are generated by the Ethernet Lite IP core upon a successful transmit or receive. The signal is synchronized to the clock domain of ciop_iob, which is responsible for sending the actual interrupt packet to the core.
I wonder why the net/uart interrupt signal is sent to the core both through ciop_iob and plic instead of just plic.
I also wonder why PITON_UART_INTR macro is not defined in ciop_iob to enable sending the packet that is related to interrupt to the core.