Interrupts in OpenPiton+Ariane

[Abdullah Yıldız]

Hi,

According to OpenPiton FPGA Prototype Manual (fpga_man):

Interrupts are generated by the Ethernet Lite IP core upon a successful transmit or receive. The signal is synchronized to the clock domain of ciop_iob, which is responsible for sending the actual interrupt packet to the core.

I wonder why the net/uart interrupt signal is sent to the core both through ciop_iob and plic instead of just plic.

I also wonder why PITON_UART_INTR macro is not defined in ciop_iob to enable sending the packet that is related to interrupt to the core.

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[Jonathan Balkind]

Hi Abdullah,

You're reading about the SPARC-specific interrupt infrastructure. The doc just hasn't been fully updated for RISC-V. For Ariane it uses the standard RISC-V PLIC and CLINT mechanisms. You can see how those are wired in chipset_impl. There might be wiring from the devices into ciop_iob but the module itself isn't being used for RISC-V.

Thanks,

Jon

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[Abdullah Yıldız]

Hi Jonathan,

Thanks for your support.

As you stated, the ciop_iob module is used in the default FPGA prototype to drive iob_packet_filter. I wanted to ask this since I am not very familiar with the OpenPiton NOC interface:

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[Jonathan Balkind]

Yeah, you can safely ignore ciop_iob for the purposes of Ariane in OpenPiton's FPGA environment.

Jon

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[Abdullah Yıldız]

OK. Thanks.

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