Accessing L2 miss counter

[Andreas Wrisley]

Hi,

I read the microarchitecture document and saw the L2 miss counter, which I would like to read. I guess that it is applicable to OpenPiton with Ariane instead of the OpenSparc mentioned in the document.

Would I be able to read these counters when running a simulation? I use "sims -sys=manycore -vlt_run -x_tiles=2 -y_tiles=1 -ariane -finish_mask 0x11 hello_world_many.c"

Can I access it by just reading the adress 0xABXX000000? Where XX contains the home node. How do I determine the home node for bits 29:24?

The result is always 0 when I try. I use 

volatile uint64_t* l2Miss = (volatile uint64_t*)0xAB00000000uL;

and then

numMisses1 = *l2Miss;

What am I missing?

Regards,

/Andreas

[Guillem López Paradís]

Dear Andreas,

-  home_node specify the tile ID/core_id where you want to read the L2 metric of interest. In your case, (-x_tiles=2 -y_tiles=1) you have a system with two Arianes so you can choose to access the L2 in core ID 0 or 1.

- About the metrics in the L2, you first need to enable them with the L2 control registers explained in the documentation:

5.4.8 Access to the L2 control register The L2 control register is a 64-bit register in L2 cache. The lowest bit is used as the enable bit for clumpy shared memory. The 2nd bit is the enable bit for the error status register. The 3rd bit is the enable bit for l2 access counter and the 4th Bit is the enable bit for l2 miss counter. 32 to 53 are used as the base address for the sharer map table (SMT). Other bits are undefined. The access format of the address is described below. :

 39:32 ⇒ access type: 0xA9 

 31:30 ⇒ undefined 

 29:24 ⇒ home node 

 23:0 ⇒ undefined 

A stx or ldx instruction can be used to read or write the data array. Each diagnostic load or store operates on the entire 64 bits

So when accessing L2 in tile 0:  

1 - STORE 0x0C00000000000000 at @0xAB00000000  --> enable the cache metrics

2 - READ 0xAA00000000 or 0xAB00000000 (access/misses)

3 you can reset them by writing zero to the latter @

Let me know if that works. We are working on a basic library to easily perform these performance counters reads.

Regards,

Guillem

 

[Andreas Wrisley]

Hi Guillem,

Thanks for your reply, I don't know how I missed the control register when reading the documentation.

I write to 0xA900000000 and I get values, although they seem a bit off.

volatile uint64_t* l2Access = (volatile uint64_t*)0xAA00000000uL;

volatile uint64_t* l2Miss = (volatile uint64_t*)0xAB00000000uL;

volatile uint64_t* l2Ctrl = (volatile uint64_t*)0xA900000000uL;

*l2Ctrl = 0x0C00000000000000uL;

*l2Miss = 0;

*l2Access = 0;

numMisses1 = *l2Miss;

...

numMisses2 = *l2Miss;

results in the following

Num misses: 0x0200000000000000, 0x9801000000000000

Num accesses: 0x0400000000000000, 0xa501000000000000

To me, this looks like I have the wrong endianness and changing gives more realistic values of 0x02, 0x0198 and 0x04, 0x01A5. I'm trying to ensure memory accesses (L2 cache misses) and looking at the numbers (if it is correct to change endianness) I don't think I made a very good job. Is there anything special in the cache hierarchy I should consider?

I'm quite new to OpenPiton/Ariane and should probably read up a bit more. Looking at the documentation, most of it is with the OpenSparc. Does everything translate to using the Ariane core? Are there other documentation focusing on the Ariane core?

I'm sorry for the slightly confused reply.

Regards,

/Andreas

[Jonathan Balkind]

Hi Andreas,

The documentation is indeed dated but should work the same for Ariane as before. Noelia just made a PR (now merged) which includes a library that you could make use of directly: https://github.com/PrincetonUniversity/openpiton/pull/144

Thanks,

Jon

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[Andreas Wrisley]

Thanks Jon, I tried the library and it is working well. It confirmed my intuition that we had to switch endianness.

/Andreas