Error in synthesis

[Yara Hesham]

Hi All,

I'm running ASIC flow and during synthesis an error appear when using link command and I don't know where I should look to solve it 

Error: Can't find inout port 'debug_req_i' on reference to 'tile' in 'chip'. (LINK-1)

Error: Unable to match ports of cell tile0 ('tile') to 'tile_TILE_TYPE2'. (LINK-25)

Thanks in advance 

[Jonathan Balkind]

My guess would be this is something about the macros that are set. debug_req_i is a port that only exists on tile when you have PITON_ARIANE or some similar macro defined. There might be a mismatch between the definition of those in chip vs in tile?

Thanks,

Jon

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