Contribution: figure with HW overview

[Marcelo Ruaro]

Hi,

In the process to understand HW architecture I made this figure showing the modules and the defines that enable/disable its respective instantiation.

Hope it be useful!

Best,

Marcelo  

[Jonathan Balkind]

Hi Marcelo,

This figure is really cool! I especially like seeing the stuff that's under macros because that's sometimes a bit hard to understand looking at the verilog alone. We were just tinkering around yesterday and having to deal with that pain a bit.

One minor thing I'd note is that the .tmp.v files are generated and the original source files are .v.pyv. You might want to indicate that somehow.

Thanks,

Jon

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