Timer interrupt

[Andreas Wrisley]

Hi,

I have a few things I'm trying to do, but I cannot seem to get it working.

1.

I'm trying to set up timer interrupts using the mtimecmp (0xFFF1024000ULL)and mtvec, but it seems I never get an interrupt. The trap handler will terminate the running application.

I'm using the pitonstream to compile and run the application.

I have it running on another CVA6-based platform (Cheshire) with the applicable address for mtimecmp of course.

Any hints on what could be wrong? Has it anything to do with how pitonstream operates?

2.

I can't get openocd to work, I get the following output:

Info : JTAG tap: riscv.cpu tap/device found: 0x00000001 (mfg: 0x000 (<invalid>), part: 0x0000, ver: 0x0)
Info : datacount=2 progbufsize=8
Error: unable to halt hart 0
Error:   dmcontrol=0x80000001
Error:   dmstatus =0x00000c82
Error: Fatal: Hart 0 failed to halt during examine()
Error: [riscv.cpu] Examination failed
Warn : target riscv.cpu examination failed
Info : starting gdb server for riscv.cpu on 3333
Info : Listening on port 3333 for gdb connections
Error: Target not examined yet

I'm using the piton/design/chip/tile/ariane/corev_apu/fpga/ariane-multi-hart.cfg (updated to work with a newer version of openocd (0.12+dev...))

I must be missing something, this I can get working with Cheshire.

3.

My ideal flow would be something like this:

- Power on, load bit file into the FPGA, 

- Pressing reset => u-boot loads my run-time and application (fit file) from TFTP and then starting the application.

I have seen discussions about booting Linux using u-boot, but I'm not quite sure where to begin. The bootrom, opensbi, u-boot stuff is still a mystery to me. Any pointers would be greatly appreciated.

Regards,

/Andreas

[Jonathan Balkind]

Hi Andreas,

1. What happens when you run your test under simulation? If it's not working there too then I might be able to share you a test I have lying around if you email me directly (iirc it doesn't have an open license as of now)

2. I'm not the most familiar with openocd issues unfortunately - hopefully someone else who has used it has some insight. Maybe something to do with different versions of the core? Did any of the mimpid or whatever CSRs change? I'm puzzled by this one but openocd has always failed with weird errors for me when it hasn't worked.

3. I'd suggest you check out the cva6-platform repo for u-boot https://github.com/openhwgroup/cva6-platform and maybe join the #u-boot channel on our zulip where we've had some recent back and forth. Wensheng set up a functioning debian image on top of the fedora image shared on that repo which we've been able to reproduce. I think it should be possible to get a driver for the xilinx ethernet to enable TFTP like you say, but the SD works quite well for u-boot stuff.

Thanks,

Jon

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