place design error after running protosyn for uart-dmw ddr

[chinmay shekhar]

Hi,

After running protosyn -b vc707 -d system --uart-dmw ddr, when i open vivado i get following 3 errors:-
[Place 30-51] IDELAYCTRL elements have been found to be associated with IODELAY_GROUP 'NET_PHY_RXC', but the design does not contain IODELAY elements associated with this IODELAY_GROUP.

[Place 30-99] Placer failed with error: 'Implementation Feasibility check failed, Please see the previously displayed individual error or warning messages for more details.'
Please review all ERROR, CRITICAL WARNING, and WARNING messages during placement to understand the cause for failure.

[Common 17-69] Command failed: Placer could not place all instances

and some critical warnings, two of them are:-
[Netlist 29-69] Cannot set property 'VCCAUX_IO', because the property does not exist for objects of type 'pin'. ["/home/esdm/project_piton/openpiton/piton/design/chipset/mc/xilinx/vc707/ip_cores/mig_7series_0/mig_7series_0/user_design/constraints/mig_7series_0.xdc":609]

[Netlist 29-69] Cannot set property 'IOSTANDARD', because the property does not exist for objects of type 'pin'. ["/home/esdm/project_piton/openpiton/piton/design/chipset/mc/xilinx/vc707/ip_cores/mig_7series_0/mig_7series_0/user_design/constraints/mig_7series_0.xdc":610]

I've gone through xilinx forum with a similar post but since i didn't make any changes in any of the module, i don't understand why i am getting this error.

[Alexey Lavrov]

Hi Chinmay,

Can you attach implementation log?

It should be located in $MODEL_DIR/vc707/system/vc707_system/vc707_system.runs/impl_1/runme.log.

From error above it is difficult to figure out the root of the problem.

Best,

Alexey

[chinmay shekhar]

Hi Alexey,

Here is the implementation log.

Thanks,
Chinmay

[Alexey Lavrov]

Hi Chinmay,

It looks to me that you are implementing design for VC707 with Ethernet controller, which this board doesn't support.

Can you tell me what the output of the next command:

cat $MODEL_DIR/genesys2/system/vivado.log | grep "Verilog defines"

It should show all defines which are used by your design. Make sure there is VC707_BOARD among them.

Alexey

[chinmay shekhar]

Hi Alexey,

Here is the result:-
 puts "INFO: Using the following Verilog defines: ${ALL_VERILOG_MACROS}"
INFO: Using the following Verilog defines: NO_SCAN FPGA_SYN PITON_FPGA_SYNTH PITON_PROTO PITON_FULL_SYSTEM PITON_FPGA_NO_DMBR SPLIT_L1_DCACHE FPGA_SYN_1THREAD FPGA_FORCE_SRAM_ICACHE_TAG FPGA_FORCE_SRAM_LSU_ICACHE FPGA_FORCE_SRAM_DCACHE_TAG FPGA_FORCE_SRAM_LSU_DCACHE FPGA_FORCE_SRAM_RF16X160 FPGA_FORCE_SRAM_RF32X80 VC707_BOARD PITON_FPGA_MC_DDR3 PITON_FPGA_SD_BOOT PITONSYS_UART_BOOT PITON_NO_CHIP_BRIDGE PITON_UART16550

Thanks,
Chinmay

On Friday, September 1, 2017 at 3:30:46 PM UTC+5:30, chinmay shekhar wrote:

[chinmay shekhar]

Hi Alexey,

Have you looked at the log i sent you? i successfully implemented openpiton with bram test, is it possible to map our own c test on bram and then test it?

Chinmay

On Friday, September 1, 2017 at 3:30:46 PM UTC+5:30, chinmay shekhar wrote:

[Alexey Lavrov]

Hey Chinmay,

I am sorry for a long response time. I was caught up in some other work.

The problem in your log is saying that there is no IDELAYE2 module even though you have in instance of IDELAYCTRL module.

These modules are instantiated in chipset.v and I can't imagine any situation when one is instantiated without another. So you probably had either logic modifications or synthesis/implementation results which were used from previous runs.

I implemented system on vc707 using protosyn -b vc707 -d system --uart-dmw ddr command without any troubles.

Can you try do it on a clean repo and tell me if you still have any problems?

Best,

Alexey