Logic Synthesis of Openpiton ASIC Flow

[Rawan Ramadan]

Hi All,

I have a question regarding synthesizing the openpiton RTL core. I don't have access to Solvnet so I can't download the Synopsys RM scripts. So my question is, should cloning the core's RTL be sufficient to run synthesis on, or some RTL files would be missing?

Thanks,

Rawan

[Jonathan Balkind]

There aren't any RTL files missing but you will need technology specific files for synthesis (ie. a standard cell library) and you will most likely want to use a memory compiler to replace the behavioural models.

Thanks,

Jon

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[Anagha Ghosh]

You might want to check out OpenLANE open-source EDA tool chain

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"A pessimist always sees difficulty in every opportunity, An optimist always sees opportunity in every difficulty"

[Manar Mahmoud]

Hi

I tried t synthesizing the openpiton RTL core but I get a lot of warnings regarding unresolvable references or missing rtl of instance used in design like mux and d_ff

after elaborate and link command for mostly each module as shown in figures bellow:

I've read all RTLs in the design and can't find these instances.

 Thanks.

 Manar

[Jonathan Balkind]

Looks like you're missing piton/design/chip/tile/common/rtl/swrvr_clib.v

Further, this is happening because you're synthesising the OpenSPARC T1 core. Is this what you intend? If not, I'd recommend you look at the macros set in build/manycore/rel-0.1/config.v after running sims for the particular build variant you're looking to use.

Thanks,

Jon

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[Rawan Ramadan]

If I want to run my own scripts, what top module should I start synthesis with?

Thanks,

Rawan

[Abdullah Yıldız]

Hi Rawan,

The top-level in OpenPiton ASIC flow is chip.

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[Manar Mahmoud]

should I include all rtl files in OCI.v then run synthesis for OCI.v since there isn't chip.v module? if not then where to start?

[Jonathan Balkind]

There is a chip module. The source file is piton/design/chip/rtl/chip.v.pyv which requires pyhp preprocessing (ie. it is not a pure verilog file so you cannot use it as input to synthesis or simulation). The preprocessing can be done by running sims. It will create piton/design/chip/rtl/chip.tmp.v which you can use directly as a verilog file

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[Jonathan Balkind]

The design is called chip, not chip.tmp

Your ${design}.v needs to be changed

On Mon, 10 May 2021 at 11:10, Manar Mahmoud <manarm.ab...@gmail.com> wrote:

Hi 

I tried to synthesis Chip.tmp.v and I have that error after elaborate command, what could be wrong?

Thank you.

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[Jonathan Balkind]

Your first command uses the lib "work" but your second uses the lib "workl". Those need to be the same. Please check for these kinds of typos when asking for outside help

On Mon, 10 May 2021 at 11:17, Manar Mahmoud <manarm.ab...@gmail.com> wrote:

I've tried this already and still not working

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