Using up-to-date cva6

[Nico Röder]

Hi,

i aim to use openpiton with cva6 as the baseline for a research project. 

However when following the instructions in the README for building the project with cva6, the ariane_build_tools.sh is running into problems due to outdated versions of the submodules. After adjusting the versions of cva6 and its according toolchains, at least verilator and the risc-v toolchain can be built, but verilator v5.008 is not able to build a simulation model with the updated cva6 core due to  syntax errors (sims.log is attached).

Is there any work in integrating up to date submodules for the current version of cva6?

Thanks in advance,

Nico 

[Pierre Bomel]

Hi Nico,

I ran into the same problem recently, with the same verilator version than yours.

Your 1rst error is:

%Error: Cannot find verilated_std.sv containing built-in std:: definitions:/home/nico/Documents/PhD/Projects/near-cache/openpiton-extensions/piton/design/chip/tile/ariane/tmp/verilator-v5.008//include/verilated_std.sv

Mine was:

%Error: Cannot find verilated_std.sv containing built-in std:: definitions:/home/bomel/princeton/cva6/tools/verilator-v5.008/include/verilated_std.sv

I did not spend time trying to understand why it did not work (but there may be an elegant solution to make it work).

I preferred to switch to the last verilator version and make a rapid try. 

Here is it my verilator's version number.

bomel@bomel-Precision-7680:~$ verilator -V
Verilator 5.045 devel rev v5.044-22-g112e1e375

I got that version from https://github.com/verilator/verilator. 

Just did a "git clone ..."

It will compile at once (at least it did on my computer) and you won't have this error again.

Sincerely, Pierre

[Nico Röder]

Hi Pierre,

thanks for you quick answer. 

After fiddling around a bit, i figured out that this error is caused by path mismatches due to the folder structure created when building verilator with the cva6 script. I fixed it by replacing the verilator root in ariane_setup.sh with this and adjusting path accordingly:

export VERILATOR_ROOT=$ARIANE_ROOT/tmp/verilator-v5.008/verilator
export VERILATOR_PATH_ADD=$ARIANE_ROOT/tmp/verilator-v5.008/bin

export PATH=$RISCV/bin:$VERILATOR_PATH_ADD:$PATH

The issue I am running into now lies in incompatibilities between the cva6 v5.3.0 and the current openpiton version, which I tried to fix by integrating some changes from this PR :  Updating CVA6 for OpenPiton and add support for HPDC #3155

However, the adjustments in the Flists and verilog files still not seem to be enough to get the system running, as there are  still some unknown signals and pins (see attached sims.log).

This one got my head stuck even more. Did you run into any similar issues after changing your verilator version?

[Pierre Bomel]

Hi Nico,

Yes I had some troubles too, but not exactly the same.

Here are my notes (I kept a record of everything to remember later) about it:

--------------------------------------------------------------------------------------------------------------------------

with verilator last version, built with openpiton env (not cva6)
sims -sys=manycore -x_tiles=1 -y_tiles=1 -vlt_build -ariane
%Error-NEEDTIMINGOPT: /home/bomel/princeton/openpiton/piton/verif/env/manycore/pc_cmp.tmp.v:661:5: Use --timing or --no-timing to specify how delays should be handled
NOK

=> add -vlt_build-args=--no-timing or -vlt_build-args=--timing
sims -sys=manycore -x_tiles=1 -y_tiles=1 -vlt_build -ariane -vlt_build_args=--no-timing
sims -sys=manycore -x_tiles=1 -y_tiles=1 -vlt_build -ariane -vlt_build_args=--timing
both create something
OK

--------------------------------------------------------------------------------------------------------------------------

Which means that the last verilator explicitely needs a timing specification now: --no-timing or --timing

Jon & Guillem helped me about that and explained me that the sims' -vlt_build_args parameter is just what I needed to add this timing specification.

So, depending on your timing requirements while simulating (I had none, any option is welcome for me) try:

sims -sys=manycore -x_tiles=1 -y_tiles=1 -vlt_build -ariane -vlt_build_args=--no-timing
or sims -sys=manycore -x_tiles=1 -y_tiles=1 -vlt_build -ariane -vlt_build_args=--timing

Pierre

[Nico Röder]

Hi Pierre, 

Good to know. Weirdly the timing is not yet an issue in my case as verilator does not even completely compile the verilog code of my project. 

Can you tell me more about your environment (which cva6 and openpiton version/ commit hash you used)? Maybe I can try the combination that worked for you and also get it running in my machine.

As a reference, I used cva6 v5.3.0 and the most recent commit of the openpiton-dev branch (it also did not work with the regular openpiton branch, that's why I changed).

Thank you for your support,

Nico 

[Pierre Bomel]

Hi Nico,

Here are my tools and versions.

PC

- Linux Ubuntu 24.04

OpenPiton

- URL = https://github.com/PrincetonUniversity/openpiton.git
- TAG = not using any specific tag or branch (so that's the last one)

RISCV GNU TOOLCHAIN

- URL = https://github.com/riscv/riscv-gnu-toolchain.git

- TAG = "2025.11.27" (last known stable version)

Unfortunately the dejagnu link was broken (dec. 2025, it may have changed since) and you'll have to download the dejagnu by yourself.

DEJAGNU

- URL = https://git.savannah.gnu.org/git/dejagnu.git

- TAG = not using any specific tag or branch

RISCV tests

- URL = https://github.com/riscv-software-src/riscv

- TAG = not using any specific tag or branch

RISCV ISA sim

- URL = https://github.com/riscv/riscv-isa-sim.git

- TAG = "35d50bc40e59ea1d5566fbd3d9226023821b1bb6" for fesvr library compilation (see OpenPiton's build scripts)

- TAG = "5f76a0d1fa68bb80560cb890405c42041f744e89" for spike compilation (see OpenPiton's build scripts)

VERILATOR: my current version is: Verilator 5.045 devel rev v5.044-22-g112e1e375

- URL = https://github.com/verilator/verilator

- TAG = not using any specific tag or branch

OPENSBI

- URL = https://github.com/riscv-software-src/opensbi.git

- TAG = v1.2

LINUX

- URL = https://github.com/Jbalkind/ariane-sdk.git

- TAG = "openpiton-opensbi"

My .bashrc contains this:

USE_OPENPITON=true
export PRINCETON=~/princeton

# RISCV gnu toolchain
export RISCV=$PRINCETON/riscv.openpiton
#export RISCV=$PRINCETON/riscv.cva6
if [ -z $RISCV ]; then
echo "RISCV variable does not exist"
else
if [ -e $RISCV ]; then
export PATH="$RISCV/bin:$PATH"
echo "RISCV toolchain is installed at $RISCV, PATH updated"
else
echo "RISCV toolchain is not installed at $RISCV"
fi
echo RISCV=$RISCV
fi

# OpenPiton
if ! [ -z $USE_OPENPITON ]; then
cd $PRINCETON/openpiton >& /dev/null
source ./piton/ariane_setup.sh
export DV_SIMULATORS=veri-testharness,spike
echo "DV_SIMULATORS=$DV_SIMULATORS"
cd - >& /dev/null
else
echo "We won't use OpenPiton"
fi

echo "PATH=$PATH"

[Pierre Bomel]

A few more comments.

To compile fesvr and spike you will need to patch device.h because the new GCC compiler is less permisive with K&R old C code.

You will just have to add an "#include <cstdint>" at the beginning of the file, or you may also add a compiler switch like -std=c99 (I preferred to add the #include).

Don't forget to update your VERILATOR_ROOT in the ariane_setup.sh file

You will have to install bison 3.5.1 (an older version of bison) and add its path first in the PATH (to avoid using the Linux' bison), or you'll get compilation errors while verilator will  compile a OpenPiton's simulation model.

I think I got bison 3.5.1 sources and installed it under /usr/local/bin.

It was absolutely necessary with verilator 4.014, I'm not sure it is still necessary with versions 5.xxx.

But, just in case, you may also try that.

Last, to be able to compile the bootrom for a simulation with verilator, you will need to update piton/design/chipset/rv64_platform/bootrom/linux/Makefile

1/ add "-std=c99" to CFLAGS

2/ remove "-march=rv64imac" to CFLAGS

All this "little issues" are coming from the natural evolution of GCC and Linux tools.

Remember Opentiton started in 2013-2015, mor ethan 10 years ago.

Be patient and persistent Nico !

Pierre

[Pierre Bomel]

I forgot to tell you about RISCV CVA6.

About my RISCV ariane/CVA6 version, I use the one that is included in the last OpenPiton's git.

I never checked what version it was.

I've also tried once with the CVA6 compiler, with some troubles about files' prefixes (gcc, gdb, ar, as, ...), and switched back to the "official" 2025.11.27 GNU toolchain version.

It does not mean CVA6 compiler would not work, but rather that I've been lazy to invest more time to install it and use it.

Pierre

[Nico Röder]

Ok, thank you. With you configuration, I now got the simulation running. Though one small change: I used the openpiton-dev branch for a slightly newer version of the cva6.

In case someone needs this in the future:

Verilator 5.045 in combination with GCC13+ requires adjustments in the 
`$VERILATOR_ROOT/include/verilated.mk`

around line 290 are rules for pch files, which need to be extended with the -c flag in order to just get compiled and not linked.

%.fast.gch: %

$(OBJCACHE) $(CXX) $(OPT_FAST) $(CXXFLAGS) $(CPPFLAGS) $(CFG_CXXFLAGS_PCH) -c $< -o $@

%.slow.gch: %

$(OBJCACHE) $(CXX) $(OPT_SLOW) $(CXXFLAGS) $(CPPFLAGS) $(CFG_CXXFLAGS_PCH) -c $< -o $@

 

If you do not do this, building the simulation model fails with the error: "undefined reference to main"

Thanks for your great and quick support.

Nico