OpenPiton Discussion

Hi Yasas, Hm interesting. I'm not sure if I have run the multithreaded tests before so I'm

Hi Yasas, Sorry that VCU118's electrical setup has caused you so much strife. It's one of the

Hi Ioannis, The special address setup isn't really going to be flexible to different designs

It's also possible that it's the test code if it's only the riscv tests and benchmarks

Hi Andreas, Yeah, UART sucks for doing any meaningful amount of data movement. My recollection is

Hm, this is not familiar to me. Generally we haven't had any major surprises of this nature, but

Thanks to Neiel, this performance issue should be fixed by the following merged PR: https://github.

Hi there, Yes, this is addressed in the README and has been asked in the group several times if you

OK, Zulipchat registered. I will go over the test cases next week. Best, Redpanda On Friday, May 16,

Thank you very much. Best, redpanda On Thursday, May 8, 2025 at 5:52:10 PM UTC+2 jbal...@ucsb.edu

Got it, reup: https://groups.google.com/g/openpiton/c/UArh-VwIcZY/m/D8AfDs-EAgAJ On Tuesday, May 6,

Thanks Jon! So in my case, in the end of the day, was the very old bitstream file (the one that's

Hey Abhay, If you navigate to piton/design/chipset/rv64_platform/bootrom/linux/Makefile, within the

Thanks Mr.Jonathan , will look into it On Thursday, March 6, 2025 at 11:21:58 PM UTC+5:30 jbal...@

Hi Andreas, I don't do much work in this area so I'm not so sure. I think I recall that Prof

Hi Uma, I think these questions have been asked and answered in some previous threads if you could do

It should be buildable from gcc source or you could use something like crosstool-ng. I'm not sure

You can go into the my_top and iob_main files and align the declaration with the use. It's just

Hi Jon, Thank you for your quick response! I've joined the group you suggested, and I really

You shouldn't rely on any specific race condition behaviour as it is purely microarchitectural

You should compile openpiton adding this new argument eg sims -sys=manycore -ariane -vlt_build -

Hi Zuhair, I think this error could be related to a bad Verilator installation or wrong configuration

This is quite a broad question. The tiles themselves will be almost the same with the exception of

I think I would need to know more about what you did and what you're seeing to give a confident

I removed awk "-e" which helped remove the problems that i was receiving in riscvlib.py.

The issue was resolved, I had a look at the Readme and the solution was provided. I am quite new to

I expect there's an error on your part if chip.tmp.v isn't including other modules (eg you

Excellent! Just a warning that when we and other users did this in the past, it wasn't uncommon

Hi Jon This is my os vesion. thanks! PRETTY_NAME="Ubuntu 22.04.3 LTS" NAME="Ubuntu

I haven't generally heard of any tool version issues for years in terms of compatibility. We run