Fwd: [time-nuts] Frequency multiplication
Bob Bownes
---------- Forwarded message ----------
From: David Armstrong <arms...@sedsystems.ca>
Date: Wed, Feb 2, 2011 at 2:17 PM
Subject: Re: [time-nuts] Frequency multiplication
To: Discussion of precise time and frequency measurement <time...@febo.com>
FPGA's do not have good jitter performance. Both Altera and Xilinx have
app notes and specs on what to expect for jitter performance.
Particularly when using high speed DACs (like the ADI AD9739) the
technique used is to drive the DAC with a good quality clock, then the
DAC drives the FPGA. With high speed dac's like this there is often a
DLL used to optimize the data edges with respect to the clock.
Similar techniques are used in the other direction ADC ._ FPGA. The
good clock is given to the DAC which presents the clock to the FPGA.
The clock out of an FPGA may be good enough depending on what you are
using it for but check carefully!
On Wed, 2011-02-02 at 10:47 -0800, Hal Murray wrote:
> > Bottom line - there's a lot to look into, and they are unlikely to help you
> > out.
>
> There are a lot of FPGAs used in DSP applications where the clock to the
> front end ADC is critical. So I'd expect there would be some in-house
> knowledge about this area. It may be that all the help you will get is
> "Don't do that."
>
> --------
>
> I think Altera uses PLLs.
>
> Xilinx uses DLLs, D for delay, a long chain of gates with an adjustable tap.
> So the output signal will jump in time when the tap switches.
>
> FPGAs are designed for digital logic rather than clock hacking. I remember
> some story from years ago about clocking troubles being traced back to input
> threshold changes due to nearby outputs switching. I forget the details. I
> think that particular problem was solved by moving all the output pins away
> from the clock input pin.
>
> The smaller FPGAs are not expensive. It might make sense to dedicate a whole
> chip to something like a clock mux.
>
> You could always use an external PLL and put the digital dividers in a FPGA.
>
>
_______________________________________________
time-nuts mailing list -- time...@febo.com
To unsubscribe, go to https://www.febo.com/cgi-bin/mailman/listinfo/time-nuts
and follow the instructions there.
tijddingen
How to get a reasonably high reference frequency with low jitter, with
a good
bang for buck ratio? (Reasonably high being in the 80 - 200 MHz
range.)
Any practical circuits for that? For example, given a good 10 MHz
reference
is the best method to do three diode doubler in cascade? When aiming
for 160
MHz is it still the most practical, or are there better schemes to
take 10
MHz in, 160 MHz out?
> To unsubscribe, go tohttps://www.febo.com/cgi-bin/mailman/listinfo/time-nuts
tijddingen
advantageous
to have a relatively high frequency low jitter reference counter that
you
count in the fpga with as little clock loading as possible. And
definitely
not through the internal DCM/PLL, which as has been pointed out add
considerable jitter.
Hence the "how to get a low jitter 80 - 160 MHz clock" to be used as
reference.