Gbit_Core_Usage

[Srkan Tran]

Hi,

I will use this IP core on Spartan-6 FPGA and 88E1111 PHY without any processor. I directly design some state machines to transmit some data and not using any core like micro blaze.

I physically (bootstrap options) configured PHY to work at GMII to Copper mode. So I initially dont need to set anything on phy. I also dont need to take any data over ethernet interface.

as far as i understand i just need to use User interface Tx control block by generating signal flow as indicated its specification document page 21.

I m using 125MHZ for mac clock, and 60 MHZ for both user and reg clock.

First i would like to learn can i use this core without scripting tools like cygwin, tcl/cl? I mean just add the core into the project and drive the user interface Tx control pins directly.

Second; is there any example for tx user interface usage in verilog?

Best regards,

[tamirci]

Hi,

isnt there any one who can give me an update? The usage of this core should not be so hard. Just missing documantation. There must be an example of MAC usage wrapper.

Best regards,

20 Temmuz 2015 Pazartesi 13:07:40 UTC+3 tarihinde tamirci yazdı:

[tamirci]

Hi,

It works now. Just need to be spend a little time. See my note on bugtracer.

Jon i m not sure if you still follow this group but thank you very much for sharing this core.

Best regards,

29 Temmuz 2015 Çarşamba 19:45:56 UTC+3 tarihinde tamirci yazdı:

[tamirci]

follow the core specification document and try to generate waves that corresponds to tx_clk, tx_en, tx_wr, tx_data.

i hope this may help you.

best regards,

28 Mayıs 2016 Cumartesi 10:15:40 UTC+3 tarihinde yyz...@163.com yazdı:

Hi,

   

    I also use this IP core on Spartan-6 FPGA and RTL8111 PHY without any processor.  I have learn nearly a month about this IP for my graduation, but I still can't debug it ,  I see you have worked well, could you share your note or your procedure, Best regards,

在 2015年7月20日星期一 UTC+8下午6:07:40，tamirci写道：