Clock frequencies clarification
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Paul Bar
Oct 8, 2014, 3:32:05 PM10/8/14
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The clock domain crossing in the Rx_FF: I had problems when using Clk_mac =125MHz, the Clk_SYS = 50MHz.
The clock domain crossing from the fast side to the slow side are done using 2 clock cycles. So at 50MHz you run into problems!
The minimum clock frequency for the user is then 125MHz/2 = 62.5MHz. The way the datasheet is written lets you believe that there is no minimum. If you can to go up to 1Gbps it must be at least 31.25MHz, but it wouldn't work at this speed.
The clock domain crossing from the fast side to the slow side are done using 2 clock cycles. So at 50MHz you run into problems!
The minimum clock frequency for the user is then 125MHz/2 = 62.5MHz. The way the datasheet is written lets you believe that there is no minimum. If you can to go up to 1Gbps it must be at least 31.25MHz, but it wouldn't work at this speed.
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