AXI4 interface for opencores-tri-mode mac

[Frans Schreuder]

Hello,

Ik have created an axi4 interface for the opencores tri mode mac. It has not been tested yet, as I am still in the process of designing my hardware to test it on, but I will do soon.
It would be nice to share my core in the opencores repository.
I see there is now an old EDK core in the repo but this is not very usable in newer designs using Vivado and 7 series Xilinx devices.

Frans

[Michael Parle]

Hi Frans,

Did you ever manage to upload this to the repo?

Mick, 

[Reese Russell]

Could you share please, I am interested in this for a school project.

[Frans Schreuder]

Hello,

Here is the Vivado IP core, it does not include the opencores mac, but just the port interface to it, the mac should be placed outside the block diagram.
Please note that this core is totally untested, I will soon get my hardware to test this on.

Kind regards,

Frans Schreuder

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[dpaul]

Hi Frans,

Thanks for uploading this.
Currently I have to implement this tri mode mac core in an Artix7 FPGA. In this context can you please confirm the following.

1> Referring to the original design by Jon, the top-module is MAC_top.v. Now you have provided here the opencore_tri_mac_v1_0.vhd (which is NEW the top-level). This instantiates opencore_tri_mac_v1_0_S00_AXI.vhd. Hence this means that MAC_top.v should be instantiated *within* opencore_tri_mac_v1_0_S00_AXI.vhd, correct?

2> How are you testing your design with the AXI4 interface?

If you don't mind we can share ideas in this forum.

Thanks in advance,
dpaul

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[Frans Schreuder]

Hello dpaul,

On Wednesday, 6 January 2016 11:01:24 UTC+1, dpaul wrote:

Hi Frans,

Thanks for uploading this.
Currently I have to implement this tri mode mac core in an Artix7 FPGA. In this context can you please confirm the following.

1> Referring to the original design by Jon, the top-module is MAC_top.v. Now you have provided here the opencore_tri_mac_v1_0.vhd (which is NEW the top-level). This instantiates opencore_tri_mac_v1_0_S00_AXI.vhd. Hence this means that MAC_top.v should be instantiated *within* opencore_tri_mac_v1_0_S00_AXI.vhd, correct?

No, if you create a block design in Vivado, you will have a few ports that you should create externally. Then the actual opencores mac can be instantiated in the external VHDL / Verilog.

2> How are you testing your design with the AXI4 interface?

If you don't mind we can share ideas in this forum.

Sure... it's not been tested yet but I will do so soon. Expect bugs!
 

[bgd...@googlemail.com]

Hi Frans,
have you already made some progress?

I would be interested in a cooperation if you still work on it!


Florian