Error while loading design, after compiling is successfully complete

[Egor Ibragimov]

Modelsim 10.5b, from Intel (Altera) Quartus 17.1

# ** Error (suppressible): (vsim-3009) [TSCALE] - Module 'MAC_tx_addr_add' does not have a timeunit/timeprecision specification in effect, but other modules do.

#    Time: 0 ps  Iteration: 0  Instance: /tb_top/U_MAC_top/U_MAC_tx/U_MAC_tx_addr_add File: ../../../../rtl/verilog/MAC_tx/MAC_tx_addr_add.v

Has anybody got this error?

[Egor Ibragimov]

Adding the line

`timescale 1 ns / 1 ns

solved this error

But why it is not in svn trunk?

How can I suggest changes by commit?