Help beginner to perform test bench of core

[m11elab...@gmail.com]

Hello,I'm trying to make test bench with Vivado but without success because Cadence  incisive is required to perform it.Now,closed Vivado and I open  Cadence and put  these files
MAC_top.v     in Core_Ethernet_35/ethernet_tri_mode/trunk/rtl/verilog
Phy_sim.v     in Core_Ethernet_35/ethernet_tri_mode/trunk/bench/verilog
User_int_sim.v     in Core_Ethernet_35/ethernet_tri_mode/trunk/bench/verilog
host_sim.v       in Core_Ethernet_35/ethernet_tri_mode/trunk/bench/verilog

and tb_top.v in /Core_Ethernet_35/ethernet_tri_mode/trunk/bench/verilog
Launching simulation i can see only the clocks variate,no other.I think I need to add stimoulus but I can't find the files that have it.
Can you help me?